The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.

The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so as to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield.

An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 m and a vertical extension in a range 100 nm to 1 m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 m to a closest one of inner corners of the groove.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

A semiconductor device includes first semiconductor regions of a first conductivity type spaced apart from each other and second semiconductor regions of a second conductivity type between adjacent first semiconductor regions. At least one second semiconductor region includes a void having at least one outer surface with a crystal plane orientation of (100). A third semiconductor region of the second conductivity type is on each second semiconductor region and a fourth semiconductor region of the first conductivity type is on the third semiconductor region. A gate electrode on is disposed on each first semiconductor region to be adjacent to a third semiconductor region via a gate insulation layer.

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

A super-junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer, a field insulator, a floating electrode layer, an isolation layer, and at least one transistor structure. The drift layer includes a plurality of n-type and p-type pillars alternately arranged in parallel to form a super-junction structure. An active region, a termination region and a transition region located therebetween are defined in the drift layer. The field insulator disposed on a surface of the drift layer covers the termination region and a portion of the transition region. The floating electrode layer disposed on the field insulator partially overlaps with the termination region. The transistor structure includes a source conductive layer extending from the active region to the transition region and superimposed on a portion of the floating electrode layer. The source conductive layer is isolated from the floating electrode layer by the isolation layer.

A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.