A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.

A semiconductor device comprising: a first electrode; a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; a fifth semiconductor region; an insulating portion that is provided between the second semiconductor region and the fifth semiconductor region and between the third semiconductor region and the fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; a second electrode; and a third electrode that is provided on the third semiconductor region and electrically connected to the third semiconductor region and the gate electrode.

A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.

A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate.