Provided is a small-sized device for measuring an oxidation-reduction potential, whereby an oxidation-reduction current and an oxidation-reduction potential can be measured by reducing noise even when a signal from a solution being measured is small. A device for measuring an oxidation-reduction potential is provided with a substrate (10), a working electrode (15) mounted on a surface of the substrate (10), and a bipolar transistor (21) for amplifying the output of the working electrode (15) also provided on the surface of the substrate (10), and the signal amplified by the bipolar transistor (21) is inputted to a processing circuit (18).

An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles.

A method of producing a silicon carbide epitaxial substrate includes steps of: preparing a silicon carbide substrate; and forming a silicon carbide layer on the silicon carbide substrate. In this production method, in the step of forming the silicon carbide layer, a step of growing an epitaxial layer and a step of polishing a surface of the epitaxial layer are repeated twice or more.

The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated semiconductor device includes a semiconductor substrate, a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, a semiconductor island in the second semiconductor layer, and a first dielectric isolation layer surrounding a bottom and sidewalls of the semiconductor island. The first dielectric isolation layer includes a first portion which is formed from a portion of the first semiconductor layer and extending along the bottom of the semiconductor island, and a second portion which is formed from a portion of the second semiconductor layer and extending along the sidewalls of the semiconductor island. The dielectrically isolated semiconductor devices needs no an SOI wafer and reduces manufacturing cost.

A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm.

An epitaxial growth apparatus includes: a reaction vessel where a semiconductor film made of silicon carbide is epitaxially grown on a substrate; a tray having a top surface, a bottom surface, and an indentation in the top surface that houses the substrate, a thickness of the tray near a center of the indentation being greater than a thickness of the tray near an edge of the indentation as measured from a bottom of the indentation to the bottom surface of the tray; and a support plate inside the reaction vessel that mounts the tray thereon so as to thermally contact the tray, thereby heating the tray.

In a circuit portion, a p.sup.+-type diffusion region penetrates, in the depth direction, an n.sup.-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p.sup.++-type contact region, an n.sup.+-type diffusion region, and a p.sup.+-type diffusion region are selectively provided in a p.sup.+-type diffusion region on the front side of the base substrate. The p.sup.+-type diffusion region penetrates the p.sup.-type diffusion region in the depth direction, on the outer periphery of the p.sup.-type diffusion region. An n.sup.+-type source region, the p.sup.+-type diffusion region, the p.sup.++-type contact region, and the n.sup.+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10.sup.5 cm.sup.2, combined with a high-purity active layer of Ga.sub.1-x-yAl.sub.xIn.sub.yN (0x1, 0y1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.