A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.

A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron gas in the first layer, a source electrode provided on the second layer, a drain electrode provided on the second layer, a gate electrode provided between the source electrode and the drain electrode on the second layer, and a first insulating layer provided between the gate electrode and the drain electrode on the second layer, the first insulating layer being a first oxide of at least one first element selected from the group consisting of Hf, Zr, Ti, Al, La, Y, and Sc, the first insulating layer containing 510.sup.19 cm.sup.3 or more of at least one second element selected from the group consisting of F, H, D, V, Nb, and Ta.

Provided is a semiconductor device including a plurality of trenches, including an emitter electrode; a floating layer of a first conduction type provided between adjacent trenches; and a low-dielectric-constant film provided between the floating layer and the emitter electrode, in which a dielectric constant of the low-dielectric-constant film is less than 3.9. Also provided is a semiconductor device further including a gate electrode formed in the trenches, in which capacitance between the gate electrode and the floating layer is greater than capacitance between the emitter electrode and the floating layer.

To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate.

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a substrate. A first insulation film is formed on the substrate. A gate electrode is formed within each trench, wherein the gate electrode partially fills each trench. A first conductivity type region is formed in the upper surface portion of the substrate between the trenches. A second conductivity type region is formed in a side surface of the substrate between the trenches and the first conductivity type region. A second insulation film is formed covering the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate. A source metal layer is formed on the second insulation film. The source metal layer is electrically connected to the first conductivity type region and the second conductivity type region.

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

A semiconductor device according to an embodiment is provided with a plurality of active barrier sections each of which is enclosed by a plurality of element isolation sections each of which is configured of a closed pattern. Namely, the plurality of active barrier sections are electrically isolated from each other.