In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process.

High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes.

In a non-insulated DC-DC converter having a circuit in which a power MOSFET high-side switch and a power MOSFET low-side switch are connected in series, the power MOSFET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOSFET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOSFET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.

An electronic device, includes: a graphene nanoribbon having a first graphene and a second graphene; a first electrode coupled to the first graphene; and a second electrode coupled to the second graphene, wherein the first graphene is terminated on an edge by a first terminal group and has a first polarity and the second graphene is terminated on an edge by a second terminal group different to the first terminal group and has a second polarity different from the first polarity.

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.