A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

In one embodiment, a trench Schottky rectifier includes a termination trench and active trenches provided in a semiconductor layer. The active trenches are configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalk and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.

A layered semiconductor includes a base layer including a substrate and a buffer layer, and a drift layer which is disposed on the base layer and is made of GaN and whose conductivity type is an n-type. The drift layer has an average n-type impurity concentration of 1.510.sup.16 cm.sup.3 or less in a radial direction of the substrate, and the difference between the maximum n-type impurity concentration and the minimum n-type impurity concentration is 1.510.sup.15 cm.sup.3 or less.

A semiconductor device is provided in which a front surface of an SiC substrate is treated before epitaxial growth so as to reduce crystal defects such as stacking faults. In an aspect, an epitaxial layer is deposited on an SiC substrate in which a periodic texture is formed in a direction perpendicular to a <1100> direction of the SiC substrate and in which an angle between a basal plane of the SiC substrate and a surface of the formed texture is smaller than an off angle.

A method for fabricating a silicon carbide power device may include steps of: forming a first n-type silicon carbide layer on top of a second n-type silicon carbide layer; depositing a first metal layer on the first silicon carbide layer; patterning the first metal layer; depositing and patterning a dielectric layer onto at least a portion of the pattered first metal layer; and depositing and patterning a second metal layer to form a Schottky barrier. In one embodiment, the first metal layer is a high work function metal layer, which may include Silver, Aluminum, Chromium, Nickle and Gold. In another embodiment, the second metal layer is called a Schottky metal layer, which may include Platinum, Titanium and Nickle Silicide.

In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.

The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other.

A switching device, such as a barrier junction Schottky diode, has a body of silicon carbide of a first conductivity type housing switching regions of a second conductivity type. The switching regions extend from a top surface of the body and delimit body surface portions between them. A contact metal layer having homogeneous chemical-physical characteristics extends on and in direct contact with the top surface of the body and forms Schottky contact metal portions with the surface portions of the body and ohmic contact metal portions with the switching regions. The contact metal layer is formed by depositing a nickel or cobalt layer on the body and carrying out a thermal treatment so that the metal reacts with the semiconductor material of the body and forms a silicide.

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.