Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein the termination trenches surrounds outer periphery of gate trenches and do not surround said gate metal pad area; Inner edges of a first termination trench of the termination trenches adjacent to trench ends of the gate trenches have a plurality of wave shape portions in regions between two adjacent trench ends of the gate trenches while outer edges have a straight shape to reduce drain-source leakage current. Each of gate trenches on which has at least one shielded gate trench contact connected to a shielded gate electrode, and the shielded gate trench contact is spaced apart from any of multiple gate metal runners with a distance larger than 100 um.

A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.

A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer.

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a well region of a first conductivity type and an isolation structure in the well region. First and second regions are respectively defined on both sides of the isolation structure. First and second gate structures are respectively disposed on the first and second regions. First and second implant regions of a second conductivity type that is different from the first conductivity type are respectively in the first and second regions and adjacent to the isolation structure. A counter implant region is in the well region under the isolation structure and laterally extends under the first and second implant regions. The counter implant region has the first conductivity type and has a doping concentration that is greater than that of the well region. A method for fabricating the high-voltage semiconductor device is also disclosed.

A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The first semiconductor fin is disposed on the semiconductor substrate, and the second semiconductor fin is disposed on the semiconductor substrate. The air gap is located between the first semiconductor fin and the second semiconductor fin, and the dielectric cap layer caps a top of the air gap.

A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.

A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.