An array substrate and a manufacturing method thereof are disclosed. The present disclosure relates to the technical field of display, whereby the qualified rate of the array substrate can be improved, and the manufacturing cost thereof can be reduced significantly. The array substrate includes a first wiring, a first insulating layer, and a second wiring from bottom up in sequence. The second wiring crosses over the first wiring. A crossed-over part of the second wiring consists of a plurality of branches, with an interspace formed between every two adjacent branches, so as to obtain a comb structure. At least one of the branches is nearer to the first wiring relative to other branches. The array substrate of the present disclosure can be used in liquid crystal TV, liquid crystal display, mobile phone, tablet personal computer, and other display devices.

A method for manufacturing an array substrate which includes: depositing a gate metal film on a base substrate, and forming a first pattern including the gate electrode by a first patterning process; depositing a gate insulating film, a first transparent conductive film, a source/drain metal film and a doped a-Si film sequentially, and forming a second pattern including the pixel electrode, the source electrode, the drain electrode and a doped semiconductor layer by a second patterning process; depositing an a-Si film, and forming a third pattern including a TFT channel, the semiconductor layer and a gate insulating layer via-hole by a third patterning process; depositing a passivation layer film, and forming a fourth pattern including a passivation layer via-hole by a fourth patterning process, the passivation layer via-hole being arranged at a position corresponding to the gate insulating layer via-hole; and depositing a second transparent conductive film on the base substrate with the fourth pattern, and forming a fifth pattern including an electrical connector by a fifth patterning process.

A manufacturing method of an AMOLED backplane includes manufacturing a TFT substrate and forming a corrugation structure on the TFT substrate, which includes raised sections and recessed sections alternating each other; coating organic photoresist on the TFT substrate that includes the corrugation structure formed thereon to form a planarization layer in such a way that an upper surface of a portion of the planarization layer corresponding to and located above the corrugation structure includes a curved configuration corresponding to the corrugation structure; forming a pixel electrode on the planarization layer in such a way that the pixel electrode shows a curved configuration; and forming, in sequence, a pixel definition layer that has an opening to expose the curved configuration and a photo spacer on the pixel electrode and the planarization layer.

The present invention discloses a conductive structure, a method of manufacturing the conductive structure, and an array substrate. The method of manufacturing the conductive structure, comprising steps of: Forming a barrier metal film and a copper metal film in this order on a substrate, wherein the copper metal film being laminated on the barrier metal film; forming a preset photoresist pattern on the copper metal film; etching the barrier metal film and the copper metal film; oxidizing an exposed sidewall of the etched barrier metal film and an exposed sidewall of the etched copper metal film, so as to generate metal oxide layers on the exposed sidewall of the etched barrier metal film and the exposed sidewall of the etched copper metal film, respectively; and stripping off the photoresist pattern by means of a photoresist stripping liquid. In the method of manufacturing the conductive structure according to embodiments of the present invention, the exposed sidewall of the conductive structure is oxidized to generate a uniform metal oxidization layer on the exposed sidewall before removing the photoresist from the conductive structure by a wet stripping process. In this way, it can effectively prevent the interfaces between the copper metal film and the barrier metal film from being separated during performing the wet stripping process.

A display panel is disclosed that includes: a base substrate, at least one via hole penetrating the base substrate, and first laser-induced graphene formed on a first surface of the base substrate adjacent to the at least one via hole.

A touch panel includes: a substrate; a first metallic layer for forming a gate of a thin-film transistor (TFT); a gate insulating layer; a second metallic layer for forming a data line, a source and a drain of the TFT; an isolation layer penetrated by a first hole; a third metallic layer for forming a driving line for transmitting a driving signal and a common voltage; a passivation layer, layered with and deposited on the isolation layer, penetrated by the first hole and a second hole, and the second hole aiming at the data line; a pixel electrode, connected to the source or the drain through the first hole; a driving electrode, connected to the driving line through the second hole; and a sensing electrode, for transmitting a sensing signal and the common voltage. The driving electrode and the sensing electrode are used as common electrode layers.

Embodiments of the disclosure provide an array substrate, a method of manufacturing an array substrate, a liquid crystal display panel, and a display device. The array substrate comprises: a common electrode and a pixel electrode on a base substrate; and a passivation layer between the common electrode and the pixel electrode. The pixel electrode is a grating structure comprising a plurality of sub-pixel electrodes. The sub-pixel electrode comprises a body structure extending in a first direction, and a bending structure extending in a second direction and formed at an end portion of at least one end of the body structure. A protrusion is disposed at a joint of the body structure and the bending structure.

A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer.

The application provides a thin film transistor, a method for manufacturing the thin film transistor, and a display panel, the thin film transistor includes a metal electrode, and a step of forming the metal electrode includes: forming a first material layer on a substrate; performing a pattering process on the first material layer to form a groove pattern in the first material layer such that the groove pattern matches with a pattern of the metal electrode to be formed; forming the metal electrode in the groove pattern such that a gap is formed between an edge of the metal electrode and an edge of the groove pattern; forming a protection pattern on the substrate formed with the metal electrode such that the protection pattern covers the metal electrode and its edge. In the application, the protection pattern is formed on the resultant metal electrode and can effectively protect conductive metal.

An array substrate, a display panel, and a fabrication method of the array substrate are provided. The array substrate comprises a first thin film transistor including a metal oxide thin film transistor, and a second thin film transistor including an amorphous silicon thin film transistor. The first thin film transistor and the second thin film transistor are disposed above a substrate. The first thin film transistor is located in a display region of the array substrate, and the second thin film transistor is located in a peripheral circuit region of the array substrate.