An array substrate for a display device includes a first base substrate; a thin film transistor disposed on the first base substrate that includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode; a first passivation layer that covers the thin film transistor and that includes an inorganic insulating material; a second passivation layer disposed on the first passivation layer that includes an exposure hole that exposes the first passivation layer on the drain electrode; a common electrode disposed on the second passivation layer; a third passivation layer that covers the common electrode and that includes a contact hole inside the exposure hole to expose the drain electrode; a cavity between the first passivation layer and the third passivation layer on the drain electrode; and a pixel electrode disposed on the third passivation layer and connected with the drain electrode.

An array substrate includes a base substrate including a display area and a peripheral area adjacent to the display area, a gate line extending in a first direction, a data line extending in a second direction crossing the gate line, a switching element electrically connected to the gate and data lines, a color filter pattern and a dummy color pattern in the display and peripheral areas, respectively, a pixel electrode on the color filter pattern, and a light blocking pattern including a black matrix pattern partially overlapping the color filter pattern and a black boundary pattern overlapping the dummy color pattern. The black boundary pattern covers the peripheral area and includes a first portion which overlaps the dummy color pattern and a second portion which does not overlap the dummy color pattern. A cross-sectional thickness of the first portion is smaller than that of the second portion.

An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.

A display of an electric device includes a plurality of separated transparent electrode blocks, which are configured to provide one or more of supplemental features such as touch recognition. Signal paths between the transparent electrode blocks and the driver for the supplemental feature are implemented with a plurality of conductive lines placed under positioned under one or more planarization layers. The conductive lines implementing the signal paths are routed across the display area, directly toward a non-display area where drive-integrated circuits are located.

An embodiment of the present invention provides a manufacturing method of an array substrate comprising forming a gate detecting pattern on the array substrate with gate lines and common electrode lines formed thereon, the gate detecting pattern being arranged on one side of a pixel region of the array substrate and used to connect all the common electrode lines for pixel units; and performing a short circuit or a open circuit detection, wherein if the difference between a signal received by a receiving terminal for a gate line and a signal transmitted from a transmitting terminal for the gate line is larger than a predetermined detection threshold value, it is determined that short circuit between the gate line and a common electrode line or open circuit in the gate line occurs.

A liquid crystal panel and manufacturing method thereof are provided. The liquid crystal panel includes: an array substrate provided with thin film transistors; a color filter substrate provided with primary photo-spacers and secondary photo-spacers. The primary photo-spacers correspond to the thin film transistors. Stage differences between the secondary photo-spacers and the primary photo-spacers decrease from the center of the panel to the boundaries thereof. Liquid crystal is filled within space between two substrates, which are then sealed. By applying a design that utilizes stage differences between the primary and secondary photo-spacers being different, optical performance decrease caused by non-uniform box thickness in different regions is prevented.

A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface.

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

Embodiments include a manufacturing method of making a semiconductor device via multiple stages of alignment bonding and substrate removal. One example is an integrated full-color LED display panel, in which multiple wafers with different arrays of LEDs are integrated onto a host wafer with driver circuitry. The driver circuitry typically is an array of pixel drivers that drive individual LEDs on the display panel.