A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component has a breakdown voltage less than a breakdown voltage of the GaN FET. The voltage dropping component is formed to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

A method of forming a stress relaxed buffer layer (SRB) on a textured or grooved silicon (Si) surface and the resulting device are provided. Embodiments include forming a textured surface in an upper surface of a Si wafer; epitaxially growing a low-temperature seed layer on the textured surface of the Si wafer; depositing a SRB layer over the low-temperature seed layer; and planarizing an upper surface of the SRB layer.

A method of forming a stress relaxed buffer layer (SRB) on a textured or grooved silicon (Si) surface and the resulting device are provided. Embodiments include forming a textured surface in an upper surface of a Si wafer; epitaxially growing a low-temperature seed layer on the textured surface of the Si wafer; depositing a SRB layer over the low-temperature seed layer; and planarizing an upper surface of the SRB layer.

A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.

The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers.

An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.

A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

A high electron mobility transistor (HEMT) includes a substrate; and a first semiconductor layer over the substrate. The HEMT further includes a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium. The HEMT further includes a top layer over the second semiconductor layer. The HEMT further includes a gate electrode over the top layer. The HEMT further includes a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.

To provide a resonant tunneling diode and a terahertz oscillator capable of further performance improvement. The resonant tunneling diode includes: a multi-quantum well structure that is composed of a group-III nitride semiconductor; a first electrode that is connected to one of sides of the multi-quantum well structure; and a second electrode that is connected to the other side of the multi-quantum well structure. The multi-quantum well structure includes a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, and a third barrier layer, which are arranged in order from the first electrode toward the second electrode. The first barrier layer, the second barrier layer, and the third barrier layer have a thickness through which a carrier can pass by a tunneling effect. The first quantum well layer and the second quantum well layer each have a potential gradient by spontaneous polarization or a sum of spontaneous polarization and piezoelectric polarization, and have mutually different thicknesses. The first quantum well layer and the second quantum well layer have compositions with different magnitudes of potential energy.

To provide a resonant tunneling diode and a terahertz oscillator capable of further performance improvement. The resonant tunneling diode includes: a multi-quantum well structure that is composed of a group-III nitride semiconductor; a first electrode that is connected to one of sides of the multi-quantum well structure; and a second electrode that is connected to the other side of the multi-quantum well structure. The multi-quantum well structure includes a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, and a third barrier layer, which are arranged in order from the first electrode toward the second electrode. The first barrier layer, the second barrier layer, and the third barrier layer have a thickness through which a carrier can pass by a tunneling effect. The first quantum well layer and the second quantum well layer each have a potential gradient by spontaneous polarization or a sum of spontaneous polarization and piezoelectric polarization, and have mutually different thicknesses. The first quantum well layer and the second quantum well layer have compositions with different magnitudes of potential energy.