A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.

A method of fabricating a vertical field effect transistor includes forming fins from a portion of a substrate. At least a first fin of the fins is associated with a first device, at least a second fin of the fins is associated with a second device. The method includes forming alternating pillars of a first polymer and a second polymer on the substrate, removing the pillars of the second polymer except between two or more fins of a same device, and forming the substrate pillars below the pillars of the first polymer. The etching creates a deep trench between the first fin and the second fin. Removing the pillars of the first polymer and any remaining ones of the pillars of the second polymer is followed by performing an oxide fill to fill the deep trench and gaps between the pillars of the substrate with oxide.

A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a substrate, conductive layers, insulating layers, a memory structure including first memory structure clusters and second memory structure clusters, isolation trenches, and common source trenches. The conductive layers and the insulating layers are interlaced and stacked on the substrate. Each first memory structure cluster include first memory structures and each first memory structure cluster include second memory structures. The first and second memory structures penetrate the conductive layers and the insulating layers. Each isolation trench is formed between a first memory structure cluster and a second memory structure cluster. The isolation trenches span horizontally on the substrate in a discontinuous manner separated by gaps. Common source trenches are formed on the substrate that run substantially parallel with the isolation trenches.

A three-dimensional stacking structure and the manufacturing method(s) thereof are described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die include contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection.

A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion.

A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2 of first partial layers and a number N2≧2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.

A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

A silicon carbide semiconductor device includes a silicon carbide semiconductor layer, a gate insulating film formed on the silicon carbide semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the gate electrode has a polysilicon layer at least on a side of an interface with the gate insulating film, and the gate insulating film has an oxide film derived from the polysilicon layer, at an interface between the gate insulating film and the polysilicon layer of the gate electrode.

A method for producing a semiconductor device includes depositing an oxide film containing an impurity having a first conductivity type on a substrate. A nitride film is deposited and a first oxide film is deposited that contains an impurity having a second conductivity type that differs from the first conductivity type. The first oxide film, the nitride film, and the second oxide film are etched to form a contact hole. An epitaxial growth process is carried out form a first pillar-shaped silicon layer in the contact hole. The nitride film is removed and epitaxial growth process is performed to form an output terminal.

There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.