A compound semiconductor device includes a compound semiconductor layer including an electron transit layer and an electron supply layer above the electron transit layer, the electron supply layer including a first layer including InAlN and a second layer including InAlGaN formed above the first layer.

A nitride semiconductor device includes: a first nitride semiconductor layer serving as an electron transit layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap greater than that of the first nitride semiconductor layer and serving as an electron supply layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer, the third nitride semiconductor layer having a band gap greater than that of the first nitride semiconductor layer and smaller than that of the second nitride semiconductor layer; and a gate part formed on the third nitride semiconductor layer, wherein the gate part has a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and includes an acceptor type impurity, and a gate electrode formed on the fourth nitride semiconductor layer.

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of In.sub.x1Al.sub.y1Ga.sub.1-x1-y1N (0x1<1, 0y1<1, 0<1x1y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of In.sub.x2Al.sub.y2Ga.sub.1-x2-y2N (0x2<1, 0y2<1, 0<1x2y21) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H.sub.0; a second semiconductor layer having a conduction band minimum E.sub.C2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H.sub.0 below the conduction band minimum E.sub.c2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.

A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride material, a barrier layer comprising a second III-Nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess. The filler element, comprising an insulating material, is disposed at least below the bottom step of the gate electrode within the gate recess. Also described are methods for fabricating such semiconductor structures. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride material, a barrier layer comprising a second III-Nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess. The filler element, comprising an insulating material, is disposed at least below the bottom step of the gate electrode within the gate recess. Also described are methods for fabricating such semiconductor structures. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.

A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.

In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d.sub.1, a lower p-doped Group III nitride layer having a thickness d.sub.2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped Al.sub.xGa.sub.1xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d.sub.2 of the lower p-doped Group III nitride layer is larger than the thickness d.sub.1 of the upper p-doped GaN layer.