A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.

A high voltage DMOS device using conventional silicon BCD (Bipolar CMOS DMOS) technology has a P-type buried layer and an N-type buried layer, a first epitaxial layer and a second epitaxial layer. The high voltage DMOS device is characterized in high breakdown voltage, good robustness and low Ron through controlling the thickness of the epitaxial layers, the dose and forming energy of the buried layers. In addition, the high voltage DMOS may further has a shallow drain region to further improve robustness.

A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second semiconductor device. The first semiconductor device includes a first gate over a first shallow well in a substrate. A first active area is in the first shallow well on a first side of the first gate. The second semiconductor device includes a second gate over a second shallow well. A third active area is in the second shallow well on a first side of the second gate. The second shallow well abuts the first shallow well in the substrate to form a P-N junction. The P-N junction increases capacitance of the semiconductor arrangement, as compared to a device without such a P-N junction.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.

There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.

An integrated circuit uses a compact CMOS device isolation scheme which forms a ring of N-well housing PMOS devices to encircle the P-well housing NMOS devices in a circuit block. An N-type buried layer is formed under the P-well and extends partially under the surrounding N-well. The compact CMOS device isolation scheme eliminates the use of a deep N-well ring around the circuit block. Therefore, the circuit blocks of the integrated circuit can be formed with reduced silicon area and the die size for implementing the integrated circuit is reduced.

A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.

A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.

A semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the STI structure and laterally between the second well region and the lateral center of the STI structure.