An imaging device including a semiconductor substrate; pixels arranged on the semiconductor substrate in a first direction; and a signal line extending in the first direction. Each of the pixels includes a photoelectric converter generating signal charge by photoelectric conversion, a charge accumulation region that accumulates the signal charge output from the photoelectric converter, a first transistor that outputs a signal to the signal line according to an amount of the signal charge accumulated in the charge accumulation region, a capacity circuit that is coupled to a gate of the first transistor and that includes a first capacitive element, the first capacitive element including a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, at least one of the first electrode and the second electrode containing a metal. The first capacitive element is closer to the semiconductor substrate than the signal line.

Provided are a solid-state imaging device, a method for driving the same and an electronic apparatus where a comparator in an AD converter in a digital pixel is characterized by low power consumption and low peak current and that are capable of operating at low voltage and achieving high linearity across the entire input range. A comparator is constituted by two stages of preamplifiers with a clamp diode and two serial current-controlling inverters, and every branch is current-controlled. The two stages of the preamplifiers and the following two consecutive inverters are all current-controlled such that low power consumption and low peak current are realized. A trade-off can be made between the noise and the comparator speed by controlling the bandwidth of the comparator using the bias current. This is beneficial to more than one comparator operation mode.

The present disclosure relates to an imaging element, a driving method, and electronic equipment that enable imaging to be performed at higher speed. The imaging element includes a pixel array in which a plurality of pixels are arranged in a matrix shape, an AD converter that performs AD conversion in parallel on pixel signals that have been output from the plurality of pixels for each column of the plurality of pixels arranged in the pixel array, and a reference signal generator that generates a reference signal that the AD converter refers to when the AD converter performs AD conversion on a pixel signal for an identical pixel signal, the reference signal having a waveform that includes a slope having a constant gradient. Then, when the AD converter performs, on the identical pixel signal, multi-sampling for performing sampling during a P-phase period and sampling during a D-phase period at least once or more, the reference signal generator generates a reference signal in which, from among a plurality of slopes during the D-phase period, a sampling period of a second slope has been set to be shorter than a sampling period of a first slope. The present technology is applicable, for example, to a CMOS image sensor including a column-parallel ADC.

An imaging array and a method of operating an imaging array are disclosed. The imaging array includes a plurality of pixel sensors. At least one of the pixel sensors includes a photodiode, and a transfer gate connecting the photodiode to a floating diffusion node, a reset circuit, and a buffer adapted to generate a voltage indicative of a potential on the floating diffusion node on a bit line. The imaging array also includes a signal generator and a controller. The signal generator controls the potential at which electrons in the photodiode well are transferred to the floating diffusion node well. The controller causes the transfer gate signal generator to lower the potential on the transfer gate during an integration period such that electrons will be transferred from the photodiode well to the floating diffusion node well if the photodiode potential is less than the floating diffusion node potential.

In a solid-state imaging element that transfers data in a vertical direction, the number of times of transfer is reduced.

The solid-state imaging element is provided with a plurality of storage units and a data transfer circuit. In the solid-state imaging element, each of the plurality of storage units is provided with a holding unit that holds predetermined reset data and signal data according to an amount of light, and an arithmetic circuit that obtains a difference between the reset data and the signal data to output as pixel data. Furthermore, the data transfer circuit in the solid-state imaging element transfers the output pixel data.

An imaging device includes first and second pixels, arranged in a first direction, each of which includes: a photoelectric converter converting incident light into signal charge; an impurity region, in a semiconductor substrate, coupled to the photoelectric converter; a first transistor having a first gate coupled to the impurity region, and first source and drain; and a second transistor having second gate, source and drain. One of the second source and the second drain is the impurity region, and another is coupled to the first source or the first drain. The imaging device further includes a signal line, coupled to the first source or the first drain, and extends along the first direction and overlaps with both of the first and second pixels. The signal line is located on an opposite side from the impurity region across a center line of the first pixel.

In a digital signal processing circuit that performs AD conversion using a comparison device and a counter, the speed of the AD conversion is increased. An attenuation unit, in a case where the level of an input signal exceeds a predetermined threshold value, attenuates the input signal and outputs it as an output signal. The comparison device compares the output signal with a predetermined reference signal that changes with lapse of time, and outputs the comparison result. The counter counts a count value until the comparison result is inverted and outputs a digital signal indicating the count value. The digital signal processing unit performs multiplication processing on the digital signal.

To suppress deterioration of image quality. A solid-state imaging device (1) according to an embodiment includes a plurality of unit pixels (100) each of which includes a photoelectric conversion element (PD) configured to generate an electric charge corresponding to an incident light quantity, a transfer transistor (102) configured to transfer the electric charge generated in the photoelectric conversion element, a charge accumulation unit (FD) configured to accumulate the electric charge transferred by the transfer transistor, an amplification transistor (105.sub.1, 105.sub.2) including at least two fingers that are connected to the charge accumulation unit in parallel, and a selection transistor (106) that is disposed corresponding to each of the fingers of the amplification transistor on a one-to-one basis.

An image sensor includes a plurality of pixel columns and a plurality of readout circuits. Each readout circuit is coupled to one of the plurality of pixel columns and includes an ADC for receiving a first analog signal of a pixel in a reset conversion phase and a second analog signal of the pixel in a signal measurement phase, a dual-ramp generator for generating a first ramp having a first ramp rate and a second ramp having a second ramp rate greater than the first ramp rate and providing the first ramp to the readout circuits in the reset conversion phase and the second ramp to the plurality of readout circuits in the signal measurement phase, and a controller configured to provide control signals to the readout circuits and the dual-ramp generator.

A photon counting device includes a plurality of pixels each including a photoelectric conversion element configured to convert input light to charge, and an amplifier configured to amplify the charge converted by the photoelectric conversion element and convert the charge to a voltage, an A/D converter configured to convert the voltage output from the amplifier of each of the plurality of pixels to a digital value and output the digital value, a correction unit configured to correct the digital value output from the A/D converter so that an influence of a variation in a gain and an offset value among the plurality of pixels is curbed, a calculation unit configured to output a summed value obtained by summing the corrected digital values corresponding to at least two pixels, and a conversion unit configured to convert the summed value output from the calculation unit to a number of photons.