A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.

A method of depositing a silicon-containing film using a film deposition apparatus is provided. The apparatus includes a turntable provided in a process chamber. In the method, a seed layer is formed on a surface of the substrate by supplying an aminosilane gas from the first process gas supplying unit for a predetermined period of time while rotating the turntable. A boron-containing gas is supplied from the first gas supplying unit to the surface of the substrate while rotating the turntable after finishing the step of forming the seed layer on the surface of the substrate. A silane-based gas is supplied from the second process gas supplying unit to the surface of the substrate while rotating the turntable and causing silicon atoms contained in the silane-based gas to bond with each other on the surface of the substrate by a catalytic action of the boron-containing gas.

A method of forming a semiconductor device includes providing a semiconductor substrate including a source/drain region, an active transistor region, and a substrate contact region coupled to a body region. A shallow trench isolation (STI) area is formed in a major surface of the semiconductor substrate in between the active transistor region and the substrate contact region. The method further includes at least partially burying at least one capacitor in the STI area.

A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

A MOS varactor includes a first N-type junction region and a second N-type junction region spaced apart from each other by a channel region, a gate insulation layer disposed on the channel region, a gate electrode disposed on the gate insulation layer, and an N-type well region including the channel region and surrounding the first and second N-type junction regions. The N-type well region exhibits a maximum impurity concentration in the channel region.

A capacitor structure is described. The capacitor structure includes a substrate; a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width; and a first and a second plurality of gates formed above the substrate. Each gate of the first and second plurality of gates having a gate width. The gate width is configured to be less than the active area width and each gate of the first and second plurality of gates is formed between a pair of source/drain regions of the plurality of source/drain regions such that the first plurality of gates interleave with the second plurality of gates.

A MOS varactor includes a first N-type junction region and a second N-type junction region spaced apart from each other by a channel region, a gate insulation layer disposed on the channel region, a gate electrode disposed on the gate insulation layer, and an N-type well region including the channel region and surrounding the first and second N-type junction regions. The N-type well region exhibits a maximum impurity concentration in the channel region.

A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.

An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.