A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites.

A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height and located on a pedestal portion of a first oxide structure. The structure further includes a second silicon fin of a second height and located on a pedestal portion of a second oxide structure. The first oxide structure and the second oxide structure are interconnected and the second oxide structure has a bottommost surface that is located beneath a bottommost surface of the first oxide structure. Further, the second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar with a topmost surface of the second silicon fin.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity. Also, thermal shunts are disposed on the substrate between adjacent transistor fingers, where the thermal shunts are electrically isolated from the transistor fingers.

A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

A method of forming a semiconductor device includes forming mesa stripe structure on a semiconductor substrate, the mesa stripe structure including a plurality of alternating trenches and mesa stripes, forming a dielectric spacer on the mesa stripe structure, and forming an etch mask on a portion of the mesa stripe structure. The etch mask covers at least a portion of a first mesa stripe of the plurality of mesa stripes. The dielectric spacer is etched to expose surfaces of the mesa stripes other than the portion of the first mesa stripe that is covered by the etch mask. The etch mask is removed, and a metal layer is formed on the mesa stripe structure. The metal layer forms metal contacts to the exposed surfaces of the mesa stripes. Related semiconductor devices are also disclosed.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.