Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

An electro-static discharge (ESD) protection unit, an array substrate, a liquid crystal display panel and a display device. The ESD protection unit includes: a thin-film transistor (TFT); a first trace; and a second trace. A gate electrode of the TFT is exposed in a region that is formed by the first trace and the second trace and corresponds to a pixel unit, and the gate electrode of the TFT is configured to collect electric charges generated between the first trace and the second trace. A source electrode of the TFT is connected to the first trace and a drain electrode of the TFT is connected to the second trace.

Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a first detector configured to detect an occurrence of an electrical over-stress between a first node to which a first voltage is applied and a second node to which a second voltage is applied, a second detector configured to detect an occurrence of an electrostatic discharge between the first and second nodes, a determination circuit configured to receive separate outputs of the first and second detectors at the same time and to generate a control signal, and a clamping device configured to perform a turn on/off operation in response to the control signal such that a voltage between the first and second nodes is clamped into a constant voltage.

An integrated circuit (IC) structure for radio frequency circuits having a grounded die seal that mitigates the effects of parasitic coupling through the die seal. Embodiments include conductive grounding ties that each electrically couple one or more of the internal grounding pads on an IC die within the magnetic loop formed by the die seal ring to an adjacent extent of an IC die seal. Induced parasitic energy within the die seal ring is quickly coupled to ground through the corresponding grounding ties and grounding pads. Accordingly, very little, if any, induced parasitic energy is propagated around the die seal ring.

The present disclosure discloses an array substrate and a method of preparing the array substrate. The method comprises providing a substrate having a display area thereon and forming a plurality of pixel structures in said display area. At least one of the plurality of pixel structures is prepared through the following procedures: forming successively, on the substrate, a patterned first metal layer which has a gate line and a floating metal pattern that is insulative to the gate line, a gate insulation layer, and a patterned second metal layer which has a data line, a source, and a drain, wherein the data line is arranged in correspondence with the floating metal pattern and spaced from the floating metal pattern through the gate insulation layer. The array substrate of the present disclosure can increase capacitance for storage of the static electricity generated in a dry plasma bombardment of the second metal layer, thus preventing electrostatic breakdown caused by insufficient capacitive storage.

An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.

The present disclosure provides a method for fabricating an array substrate. The method includes providing a substrate; forming a first pattern on the substrate including a plurality of signal lines and a plurality of electrostatic discharge (ESD) lines, wherein an ESD line is configured to connect two signal lines; and removing a portion of each ESD line during a process for forming a second pattern over the first pattern to disconnect the two signal lines.

A display substrate and a display device are provided. The display substrate includes: plural gate lines each having at least one end provided with plural first electrostatic discharge (ESD) units configured to discharge static electricity in the gate lines. The plural first ESD units have curvatures different from each other. By discharging the static electricity through the plural ESD units, in case one of the ESD units is broken down by electrostatic current, the other ones can continue working.

In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.