A gallium oxide substrate includes first and second main surfaces. When measured data z.sub.0(r,) of height differences of points (r,,z) on the first main surface from a least square plane of the first main surface are approximated by a function z(r,)=a.sub.nmz.sub.nm(r,), a ratio of a first maximum height difference of a component of z(r,) obtained by summing terms a.sub.nmz.sub.nm(r,) with an index j of 4, 9, 16, 25, 36, 49, 64, and 81, when the second main surface is placed facing a horizontal flat surface, to a diameter of the first main surface is 0.3910.sup.4 or less, and a ratio of a second maximum height difference of a component of z(r,) obtained by summing terms a.sub.nmz.sub.nm(r,) with j of from 4 to 81, when an entire surface of the second main surface is adsorbed to a flat chuck surface, to the diameter is 0.5910.sup.4 or less.

A gallium oxide substrate includes first and second main surfaces. When measured data z.sub.0(r,) of height differences of points (r,,z) on the first main surface from a least square plane of the first main surface are approximated by a function z(r,)=a.sub.nmz.sub.nm(r,), a ratio of a first maximum height difference of a component of z(r,) obtained by summing terms a.sub.nmz.sub.nm(r,) with an index j of 4, 9, 16, 25, 36, 49, 64, and 81, when the second main surface is placed facing a horizontal flat surface, to a diameter of the first main surface is 0.3910.sup.4 or less, and a ratio of a second maximum height difference of a component of z(r,) obtained by summing terms a.sub.nmz.sub.nm(r,) with j of from 4 to 81, when an entire surface of the second main surface is adsorbed to a flat chuck surface, to the diameter is 0.5910.sup.4 or less.

In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface, and at least one transistor device structure. A source pad and a gate pad are arranged on the first major surface. A drain pad and at least one further contact pad are coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface, and at least one transistor device structure. A source pad and a gate pad are arranged on the first major surface. A drain pad and at least one further contact pad are coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

A support layer substrate, a composite substrate and an electronic device are provided. The support layer substrate has a main support surface, each sampling area on the main support surface achieves a target roughness, and each sampling area is defined as an area with a length and a width each smaller than or equal to 400 m. The target roughness is represented by a maximum peak height after Gaussian filtering of smaller than 20 nm, and the target roughness is represented by an arithmetic mean height after Gaussian filtering of smaller than 0.7 nm. The support layer substrate can achieve better bonding results and improve a bonding efficiency. The obtained composite substrate has higher bonding strength and a high production yield, thereby ensuring quality of the electronic device and reducing production costs.

A power semiconductor device includes a substrate, an epitaxial layer, a barrier layer, a channel layer, a source pin and a drain pin, and a gate structure. The epitaxial layer is over the substrate and has a top surface that is a rough interface or a capture interface doped with ions. The rough interface is used to disrupt the atomic structure of the top surface, thereby breaking down the two-dimensional electron gas. The ions doped in the capture interface are used to trap the two-dimensional electron gas. The barrier layer is in contact with the top surface of the epitaxial layer. The channel layer is disposed on the barrier layer. The source pin and the drain pin are respectively disposed on two sides of the channel layer. The gate pin is disposed over the channel layer.

A silicon carbide epitaxial substrate has a silicon carbide substrate, a silicon carbide epitaxial layer, an internal line-shaped stacking fault, and a carrot defect. The silicon carbide epitaxial layer is located on the silicon carbide substrate and has a main surface. The internal line-shaped stacking fault is located inside the silicon carbide epitaxial layer and is separated from the main surface. The carrot defect is exposed at the main surface. A value obtained by dividing a length of the internal line-shaped stacking fault by a width of the internal line-shaped stacking fault is 0.5 or less. A value obtained by dividing a length of the carrot defect by a width of the carrot defect is more than 0.5. The number of the internal line-shaped stacking faults is less than the number of the carrot defects.

A substrate structure includes an inorganic substrate, an adhesion promotion layer (APL), an electroless nickel-phosphor layer, and a conductive material. The inorganic substrate has an upper surface, a lower surface, and at least one through hole. The APL is disposed on the upper surface, the lower surface, and an inner wall of the at least one through hole. The electroless nickel-phosphor layer is disposed on a portion of the APL. The conductive material is disposed on the electroless nickel-phosphor layer and fills the at least one through hole to define at least one first conductive circuit on the upper surface, at least one second conductive circuit on the lower surface and at least one conductive through hole located within the at least one through hole and electrically connected to the at least one first conductive circuit and the at least one second conductive circuit.

A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.

A semiconductor structure includes a silicon carbide substrate and an epitaxial layer. A top surface of the silicon carbide substrate has a plurality of recesses, a bottommost portion of each of the recesses, has a first inclined surface and a second inclined surface connected with each other, and an angle between the first inclined surface and the second inclined surface is 88 degrees to 92 degrees. The epitaxial layer is disposed on the top surface of the silicon carbide substrate.