An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

An oxide superconductor includes: REBa.sub.2Cu.sub.3O.sub.7-x (RE being one element selected from a “RE element group” of Pr, Nd, Sm, Eu, Gd, Y, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The RE includes at least three, types of metallic elements (M1, M2, and M3), and the three types of metallic elements are any element of the RE element group selected in order. In an oxide system satisfying R(1)≦20 mol % and R(M2)≧60 mol % and R(M3)≦20 mol %, R(M1) being an average metallic element ratio of M1 in M1+M2+M3, SD(Ms)>0.15 is satisfied at a position at 50% of an average film thickness of a cross section including the c-axis, Ms being the metallic element of not larger of R(M1) and R(M3), SD(Ms) being a standard deviation/average value of a concentration of Ms.

A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.

A superconducting wire rod according to an aspect of the present disclosure is a superconducting wire rod having a flat cross-sectional shape which is characterized in that a voltage is generated with a lower current density or a higher voltage is generated with the same current density in a region on at least one end side in a wire rod width direction as compared with a region other than the region on the at least one end side.

Methods and devices for producing reinforced 2212 multifilament superconducting wire with low aspect shape. More specifically, methods and devices for producing reinforced round or rectangular wire with reinforcement strips. Methods and devices for producing cable using the reinforced 2212 multifilament superconducting wire as well as for producing reinforced 2223 Silver tape-based cable.

A configuration and a method of constructing a high-temperature superconductor tape including a plurality superconducting filaments sandwiched between a substrate and an overlayer, and having a compliant material extending between the substrate and the overlayer and isolating each superconducting filament.

A phase quantum bit is disclosed. In one embodiment, the phase quantum bit may comprise a Josephson junction and a distributed element coupled to the Josephson junction. The distributed element provides a capacitive component and an inductive component of the phase quantum bit.

A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a base electrode in the first dielectric layer with the base electrode having a top surface aligned with the top surface of the first dielectric layer. The method further comprises forming a Josephson junction (JJ) over the base electrode, depositing a second dielectric layer over the JJ, the base electrode and the first dielectric layer, and forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and a second contact through the second dielectric layer to a second end of the JJ.

According to various implementations of the invention, high quality a-axis XBCO may be grown with low surface roughness. According to various implementations of the invention, low surface roughness may be obtained by: 1) adequate substrate preparation; 2) calibration of flux rates for constituent atoms; and/or 3) appropriate control of temperature during crystal growth. According to various implementations of the invention, a wafer comprises a smoothing layer of c-axis XBCO; a first conducting layer of a-axis XBCO formed on the smoothing layer; an insulating layer formed on the first conducting layer; and a second conducting layer of a-axis XBCO formed on the insulating layer, where, for a same surface roughness, a thickness of the smoothing layer and the first conducting layer combined is greater than a thickness of the first conducting layer without the smoothing layer.

A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.