A semiconductor device includes a first transistor including a first drain/source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain/source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer.

A method includes forming a first semiconductor layer and a second semiconductor layer vertically above the first semiconductor layer over a substrate; forming a first ferroelectric layer and a second ferroelectric layer wrapping around the first semiconductor layer and the second semiconductor layer, respectively; forming a first gate structure and a second gate structure over the first ferroelectric layer and the second ferroelectric layer, respectively, wherein the first gate structure is in contact with the second gate structure; and forming a conductive feature electrically connecting a drain region of the first semiconductor layer with a drain region of the second semiconductor layer.

According to various example embodiments, a semiconductor element includes: a channel layer including a semiconductor material; a p-type semiconductor layer and an n-type semiconductor layer apart from each other with the channel layer therebetween, a paraelectric layer on a first area of the channel layer, a ferroelectric layer on a second area different from the first area of the channel area, and having a polarization state due to a voltage applied from an external source, a first gate electrode on the paraelectric layer, a second gate electrode on the ferroelectric layer, and an insulating layer between the first gate electrode and the second gate electrode, and electrically separating the first gate electrode and the second gate electrode from each other.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel provided with a first switching element, a first column channel connected to the first row channel and provided with a second switching element, a connecting channel connecting the pad to the first row channel or the first column channel, a second row channel connected with the pad through a third switching element and a second column channel connected with the pad through a fourth switching element. The first row channels with the same row position are connected to each other, and the second row channels with the same row position are connected to each other. The first column channels with the same column position are connected to each other, and the second column channels with the same column position are connected to each other.

A system, method and apparatus include one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations for hardware-accelerated execution of a genomic data processing pipeline based on one or more user-selectable options presented via a graphical user interface. The operations include obtaining first data representing a selection of one or more of a plurality of user-selectable options submitted via the graphical user interface. One or more of the plurality of user-selectable options identify a particular genomic data processing pipeline. The operations further include configuring, using the application programming interface executed by the one or more computers, an integrated circuit to perform one or more hardware accelerated steps of a primary, secondary, and/or tertiary processing protocol of the particular genomic data processing pipeline.