A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.

An obtained margin is smaller than a margin to be kept for a fault period predicted by life prediction based on a power cycle test, extending a maintenance cycle for replacement and so on. A method of detecting a fault of a semiconductor device including a power device mounted on a metal base and a drive circuit for driving the power device, the method detecting a fault of the semiconductor device beforehand based on an increase in thermal resistance between the metal base and the power device. A state of the power device is measured immediately before and after the power device is driven by the drive circuit. A temperature difference of the power device before and after driving is calculated according to the result of measurement. An increase in thermal resistance between the metal base and the power device is detected based on the temperature difference and an amount of electricity inputted to the power device in the driving period, and a fault of the semiconductor device is detected beforehand according to the increase.

Electrical current and/or conductivity in an electrical current channel varies in response to spatiotemporal magnetic flux pattern and/or to variation in electromotive force (EMF). For example, a channel with time-varying electrical conductivity can have induced electrical current variation due to flux pattern resulting from electrical current in another channel or set of channels; the current variation can increase magnetic flux density. The electrical currents can be transient electrical currents, and can cascade to amplify a resulting electromagnetic waveform. A channel can include the channel of a zener or zener-like diode or of a transistor, as well as an extended conductive channel. Channels can be configured in electrical current loops and in various orientations and combinations to obtain current and/or conductivity variation. A transient electrical current can be triggered in a channel, e.g. by an EMF peak, and circuitry with a combination of EMF triggering components can perform logical and timing operation.

In one general embodiment, a structure includes a first diode, comprising: a first layer having a first type of dopant, and a second layer above the first layer, the second layer having a second type of dopant that is opposite to the first type of dopant. A second diode is formed directly on the first diode. The second diode comprises a first layer having a third type of dopant and a second layer above the first layer of the second diode, the second layer of the second diode having a fourth type of dopant that is opposite to the third type of dopant. In another general embodiment, a process includes a repeated sequence of growing a first layer having a first type of electrically active dopant and growing a second layer having a second type of electrically active dopant that is opposite to the first type of dopant.

In one general embodiment, a structure includes a first diode, comprising: a first layer having a first type of dopant, and a second layer above the first layer, the second layer having a second type of dopant that is opposite to the first type of dopant. A second diode is formed directly on the first diode. The second diode comprises a first layer having a third type of dopant and a second layer above the first layer of the second diode, the second layer of the second diode having a fourth type of dopant that is opposite to the third type of dopant. In another general embodiment, a process includes a repeated sequence of growing a first layer having a first type of electrically active dopant and growing a second layer having a second type of electrically active dopant that is opposite to the first type of dopant.

A semiconductor die includes: a semiconductor substrate; a power transistor formed in the semiconductor substrate; a current sense device formed in the semiconductor substrate and occupying less area of the semiconductor substrate than the power transistor; a first contact pad electrically connected to a first load terminal of the power transistor; a second contact pad electrically connected to a sense terminal of the current sense device, the second contact pad being dedicated to current sensing only; and a resistive and/or diodic connection between the sense terminal of the current sense device and the first load terminal of the power transistor. The resistive and/or diodic connection is designed solely for ESD (electrostatic discharge) protection of the current sense device, by providing an ESD discharge path to the first load terminal of the power transistor.

An electrical feedback barrier is configured to safely interconnect an intrinsically safe power supply to a non-intrinsically safe electrical load device in a hazardous environment. Electrical feedback from the non-intrinsically electrical load device is blocked by the electrical feedback barrier to protect the intrinsically safe power supply from adverse operating conditions. The electrical feedback barrier and the electrical load device are enclosed in an explosion-proof or flameproof enclosure for compliance with electrical equipment safety standards in the hazardous environment.

An electrical feedback barrier is configured to safely interconnect an intrinsically safe power supply to a non-intrinsically safe electrical load device in a hazardous environment. Electrical feedback from the non-intrinsically electrical load device is blocked by the electrical feedback barrier to protect the intrinsically safe power supply from adverse operating conditions. The electrical feedback barrier and the electrical load device are enclosed in an explosion-proof or flameproof enclosure for compliance with electrical equipment safety standards in the hazardous environment.

The invention provides an electronic cascode power device. The electronic cascode power device has a high-side terminal, a low-side terminal and a control terminal. The electronic cascode power device comprises: a high-voltage silicon (Si) super-junction MOSFET with a drain connected to the high-side terminal of the cascode device; a low-voltage gallium nitride (GaN) HEMT with a drain connected to a source of the high-voltage Si super-junction MOSFET, a source connected to the low-side terminal of the cascode device and a gate connected to the control terminal of the cascode device; and an overvoltage clamping circuit connected between the drain and source of the low-voltage GaN HEMT. The provided cascode structure can effectively suppress the reverse-recovery process of super-junction MOSFET, achieving nearly 50% reduction in overall switching loss at high current levels.

The invention provides an electronic cascode power device. The electronic cascode power device has a high-side terminal, a low-side terminal and a control terminal. The electronic cascode power device comprises: a high-voltage silicon (Si) super-junction MOSFET with a drain connected to the high-side terminal of the cascode device; a low-voltage gallium nitride (GaN) HEMT with a drain connected to a source of the high-voltage Si super-junction MOSFET, a source connected to the low-side terminal of the cascode device and a gate connected to the control terminal of the cascode device; and an overvoltage clamping circuit connected between the drain and source of the low-voltage GaN HEMT. The provided cascode structure can effectively suppress the reverse-recovery process of super-junction MOSFET, achieving nearly 50% reduction in overall switching loss at high current levels.