A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.

A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.

A semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type differing from the first conductivity type in the first semiconductor layer; a third semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type having the same impurity concentration distribution as the third semiconductor layer in a depth direction.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

An electronic device includes an n-type substrate having a first concentration of n-type dopants, an intrinsic epitaxial layer on the n-type substrate having a second concentration of n-type dopants that is less than the first concentration of n-type dopants, an n-type epitaxial layer on the intrinsic epitaxial layer having a third concentration of n-type dopants that is greater than the second concentration of n-type dopants, and a p-type epitaxial layer on the n-type epitaxial layer. A method includes growing an intrinsic epitaxial layer having a second concentration of n-type dopants on an n-type substrate having a higher first concentration of n-type dopants, growing an n-type epitaxial layer having a third concentration of n-type dopants on the intrinsic epitaxial layer, the third concentration of n-type dopants being greater than the second concentration of n-type dopants, and growing a p-type epitaxial layer on the n-type epitaxial layer.

A method forms an integrated circuit, by steps including forming a polysilicon layer having a first side over a semiconductor substrate having a top surface, forming over the semiconductor substrate a first resist layer having a second side spaced apart from the first side, forming a diode well extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type, forming over the semiconductor substrate a second resist layer having a third side, and forming a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending from the diode well along the top surface.

A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

A capacitor structure comprises a first conductive region having a first conductivity type and a second conductive region having a second conductivity type different than the first conductivity type. The first conductive region comprises a first protrusion portion and a second protrusion portion. The second conductive region comprises a protrusion portion. The capacitor structure further comprises a first dielectric overlying the first protrusion portion of the first conductive region, and a first conductor overlying the first dielectric. Additionally, the capacitor structure comprises a terminal of a diode overlying the second protrusion portion of the first conductive region and the protrusion portion of the second conductive region. The terminal of the diode comprises a second conductor isolated from the first conductor.