A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. A DTI region is formed in a trench that penetrates through the p-type semiconductor layer and the n-type buried layer, reaching the p-type substrate region. A plurality of scallops are formed at a side surface of the trench. A size of each of a plurality of first scallops formed at the side surface of the trench in the p-type semiconductor layer is larger than a size of each of a plurality of second scallops formed at the side surface of the trench in the n-type buried layer.

A Zener diode includes a P+ anode, a poly mesh ring residing on the surface of the semiconductor substrate and surrounding the P+ anode, an N+ cathode residing opposite the poly mesh ring from the P+ anode, an outer spacer on an outer portion of the poly mesh ring adjacent the N+ cathode, and an inner spacer on an inner portion of the poly mesh ring adjacent to the P+ anode. The poly mesh ring may be a polysilicon layer residing upon a TEOS layer. The Zener diode may reside in a low dope N-well with a Zener junction including a N-well high region adjacent and below the P+ anode. The Zener diode may reside in a high dope N-well with a Zener junction including a P structure formed in the high dope N-well in an upper portion of the semiconductor substrate and adjacent and surrounding the P+ anode.