A semiconductor apparatus can block the voltage from the power source when the voltage from the power source reaches an excessive level, without requiring a larger chip size. Provided is a semiconductor apparatus including a power semiconductor element a gate of which is controlled in response to a control signal, an overvoltage detector configured to detect that a voltage at a collector terminal of the power semiconductor element reaches an overvoltage level, and a block unit configured to, in response to the detection of the overvoltage level, control the gate of the power semiconductor element to transition to an off-voltage. The semiconductor apparatus may further include a reset unit configured to, in response to that the control signal is input that turns on the power semiconductor element, output a reset signal for a predetermined period of time.

A light emitting diode package for a directional display may comprise light emitting diodes and a protection diode. The protection diode may be arranged in a well that is at a different location to the well that the light emitting diodes are arranged. The directional display may include a waveguide. The waveguide may include light extraction features arranged to direct light from an array of light sources by total internal reflection to an array of viewing windows and a reflector arranged to direct light from the waveguide by transmission through extraction features of the waveguide to the same array of viewing windows. The brightness of the directional display can be increased. An efficient and bright directional display system can be achieved. Efficient light baffling for light escaping from the edge of the waveguide is achieved through light deflecting extraction films.

An ESD protection device comprising an SCR-type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area of an N-type well. One or more diodes connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers between doped regions instead of gate oxide technology significantly reduces unwanted leakage currents.

An LED package structure includes a substrate, a circuit layer and an insulating layer both disposed on the substrate, a light-emitting unit, and a reflective housing integrally formed with the insulating layer. The light-emitting unit includes an LED chip and a fluorescent body encapsulating the LED chip. The light-emitting unit is mounted on the insulating layer and the circuit layer. The fluorescent body of the light emitting unit is spaced apart from the circuit layer with a gap in a range of 310 m. The reflective housing is formed on the insulating layer and the circuit layer and is further filled within the gap. A top plane of the reflective housing arranged away from the substrate is lower than or equal to that of the light-emitting unit, and a distance between the two top planes is in a range of 030 m.

The present invention provides a light-emitting diode (LED) chip. The LED chip includes a LED structure and an electrostatic discharge (ESD) protection structure. The ESD protection structure is in a corner of the LED chip and connects with the LED structure in anti-parallel. An interface between the LED structure and the ESD protection structure is a straight line from a top view.

A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.

An overvoltage protection device includes a resistor that is connected in series between an internal signal line connected to a communication terminal of a processor and a communication line, a diode of which a cathode is connected to the internal signal line and an anode is connected to a ground, and a PNP transistor of which a base is connected to a power supply terminal, an emitter is connected to the internal signal line, and a collector is connected to the ground. When a base-emitter voltage (a junction saturation voltage) of the transistor in operation is defined as VBE and a power source is turned on (a voltage V1) by the operation of the transistor, a voltage of the internal signal line is limited to the source voltage V1+VBE. When the power source is turned off (a voltage 0 V), the voltage of the internal signal line is limited to the source voltage 0 V+VBE.

In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.

A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.

A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.