A silicon carbide substrate has a main surface. The main surface is constituted of an outer peripheral region and a central region. The outer peripheral region is a region within 5 mm from an outer edge of the main surface. The central region is surrounded by the outer peripheral region. A standard deviation of lifetimes of minority carriers in the central region is 0.7 ns or less. A standard deviation of lifetimes of minority carriers in the central region before a process of heating to a temperature 1600- C. to 1900 C. is performed is defined as a first standard deviation. A standard deviation of lifetimes of minority carriers in the central region after the process is performed is defined as a second standard deviation. A value obtained by subtracting the first standard deviation from the second standard deviation is 10% or less of the first standard deviation.

A thin film transistor 101 includes: an active layer 7 that is supported on a substrate 1 and includes a first region 7S, a second region 7D and a channel region 7C located between the first region and the second region; a gate electrode 11 that is arranged so as to overlap with at least the channel region of the active layer 7 with a gate insulating layer 9 therebetween; a source electrode 15s electrically connected to the first region 7S; and a drain electrode 15d electrically connected to the second region 7D, at least the channel region 7C of the active layer 7 having a layered structure that includes a first metal layer m1 arranged on a lower oxide semiconductor layer 71 and containing substantially no oxygen, and an upper oxide semiconductor layer 72 arranged on the first metal layer m1, wherein a thickness of the first metal layer m1 is smaller than a thickness of the lower oxide semiconductor layer 71 or the upper oxide semiconductor 72.

A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film. Further, the semiconductor device includes an emitter region of an n-type provided in the semiconductor substrate, exposed on the front surface of the semiconductor substrate, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film provided on the inner surface of the intersection of the first trench and the second trench.

With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.

The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

Methods, systems, and computer program products for managing Internet of Things (IoT) network-connected devices.