A semiconductor device according to an embodiment includes a semiconductor chip having a transistor region and a diode region, and a conductor. The semiconductor chip includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and a gate electrode. The first electrode includes a first region in the transistor region and a second region in the diode region. A first contact area between the conductor and the first region is larger than a second contact area between the conductor and the second region.

A switching element has a gate electrode in a trench of an element part having a central portion and an outer peripheral portion. The element part has an n-type source region. The outer peripheral portion has a p-type body region, an n-type drift region, and p-type electric field relaxation regions disposed at an interval in a lateral direction of the semiconductor substrate, within a depth range including a lower end or below the lower end of the trench. The drift region is located within the interval between the electric field relaxation regions. A value obtained by dividing a width of the electric field relaxation region in the lateral direction by a width of the interval between the electric field relaxation regions is larger in the outer peripheral portion than in the central portion.

The present disclosure describes non-classical (e.g., quantum) computing systems and methods that utilize dopant molecules contained in host materials as qubits. The dopant molecules generally comprise ground-state triplet (GST) molecules, such as carbenes or nitrenes. The host materials generally comprise organic molecules. Precursors to the dopant molecules can be embedded in the host materials and then subjected to ultraviolet (UV) or visible light to form dilute molecular crystals comprising the dopant molecules embedded in the host materials. The triplet sub-levels of the dopant molecules may be manipulated using electromagnetic (EM) radiation such as optical, radiofrequency (RF), and/or microwave (MW) radiation to conduct non-classical computing operations.

In a method of manufacturing a silicon carbide semiconductor device having a switching element on a semiconductor substrate made of silicon carbide to have a built-in diode, measuring a BPD density which is a density of basal plane dislocation in the semiconductor substrate; predicting an energization fluctuation quantity based on at least the BPD density, the energization fluctuation quantity being an amount of fluctuation in electrical characteristics after the switching element is driven for a predetermined time relative to an initial value of electrical characteristics of the switching element immediately after a semiconductor chip having the switching element is manufactured; and determining whether or not to continue manufacturing the silicon carbide semiconductor device using the semiconductor substrate based on the energization fluctuation quantity.

Provided is a semiconductor device manufacturing method including forming a buffer region of a first conductivity type by implanting hydrogen ions into a semiconductor substrate. In forming the buffer region, a peak in a doping concentration is formed at a first position in a depth direction of the semiconductor substrate, and also a lifetime control region, in which a carrier lifetime is reduced by implanting the hydrogen ions, is formed at a second position on a side of an upper surface of the semiconductor substrate relative to the first position in the depth direction.

Provided is a semiconductor device manufacturing method including forming a buffer region of a first conductivity type by implanting hydrogen ions into a semiconductor substrate. In forming the buffer region, a peak in a doping concentration is formed at a first position in a depth direction of the semiconductor substrate, and also a lifetime control region, in which a carrier lifetime is reduced by implanting the hydrogen ions, is formed at a second position on a side of an upper surface of the semiconductor substrate relative to the first position in the depth direction.

A method is provided for operating a fractional quantum Hall apparatus including a set of interferometers, each having a cell and a set of gate electrodes located around the cell. The method includes calibrating each one of the interferometers to confine a droplet of a 2D charge carrier gas in a fractional quantum Hall effect state of filling factor 17/5 or 12/5, while a reentrant phase of integer quantum Hall effect states of the 2D charge carrier gas is located between the area of the droplet in a fractional quantum Hall effect state and the interferometer electrodes. The calibrating includes setting a value of a magnetic field across the apparatus such that the reentrant phase and the droplet of the 2D charge carrier gas are present in at least one of the interferometers based on interference measurements on at least one of the interferometers for different values of the magnetic field.

A method of manufacturing a semiconductor device includes: implanting a first conductivity type impurity into a SiC substrate; and implanting a second conductivity type impurity into the SiC substrate. A concentration distribution of the first conductivity type impurity has a reduction region, in which the concentration of first conductivity type impurity continuously decreases as moving away from a first peak value. A concentration distribution of the second conductivity type impurity has a second peak value. The second peak value overlaps with a specific region within the reduction region that has a first conductivity type impurity concentration that is 10% or more of the first peak value. The position of the first peak value is the first conductivity type region. At least a part of the specific region is the second conductivity type region.

A semiconductor device has a gate electrode in a trench. The semiconductor substrate has: a first n-type region in contact with the gate insulating film; a p-type upper body region in contact with the gate insulating film below the first n-type region; an n-type barrier region in contact with the gate insulating film below the upper body region; a p-type lower body region in contact with the gate insulating film below the barrier region; a connection portion electrically connecting the barrier region and the upper electrode; an n-type drift region in contact with the gate insulating film below the lower body region; and a second n-type region in contact with the lower electrode. A lower portion of the gate insulating film is thicker than an upper portion of the gate insulating film.

An apparatus includes a first wall and a second wall extending from a planar surface of a substrate to a wall height, and a plurality of electrodes disposed on the first wall and the second wall. The first wall and the second wall can be spaced apart from one another along a first axis on the planar surface. The plurality of electrodes can be configured to generate an electric field to trap an ion at a trapping position located between the first wall and the second wall. A vertical distance between the trapping position and the planar surface of the substrate can be smaller than the wall height.