A 3D imaging system includes an optical modulator for modulating a returned portion of a light pulse as a function of time. The returned light pulse portion is reflected or scattered from a scene for which a 3D image or video is desired. The 3D imaging system also includes an element array receiving the modulated light pulse portion and a sensor array of pixels, corresponding to the element array. The pixel array is positioned to receive light output from the element array. The element array may include an array of polarizing elements, each corresponding to one or more pixels. The polarization states of the polarizing elements can be configured so that time-of-flight information of the returned light pulse can be measured from signals produced by the pixel array, in response to the returned modulated portion of the light pulse.

A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged on a semiconductor substrate, in which each of the pixels includes a photoelectric converting portion and a charge converting portion for converting a charge generated by photoelectric conversion into a pixel signal and blooming is suppressed by controlling a substrate voltage of the semiconductor substrate.

A solid-state image pick-up apparatus of an example includes a photoelectric conversion portion, a transfer transistor configured to transfer a charge in the photoelectric conversion portion, and a signal output circuit configured to supply selectively a first voltage to turn on the transfer transistor and a second voltage to turn off the transfer transistor to the transfer transistor. The signal output circuit is configured to supply the second voltage having a voltage value selected from two or more different voltage values based on an output signal from a pixel.

An imaging pixel may be operated in either a linear mode or a logarithmic mode. In the logarithmic mode, the voltage at a floating diffusion region may be proportional to the logarithm of the intensity of incident light. In order to enable correlated double sampling (CDS) in the logarithmic mode, a transistor may be provided that couples the photodiode to a bias voltage. When the transistor is turned off, the photodiode may be able to operate in a logarithmic mode. When the transistor is turned on, the floating diffusion region may be reset to a baseline voltage level. Images from the linear mode and the logarithmic mode may be combined to form high dynamic range images with flicker mitigation.

An image pixel may include a photodiode, storage node, floating diffusion, and capacitor. A first transistor may be coupled between the photodiode and the storage node. A second transistor may be coupled between the storage node and the floating diffusion. A third transistor may be coupled between the capacitor and the floating diffusion. A potential barrier may be formed between the storage node and the capacitor. The potential barrier may exhibit a potential that is between the potential of the photodiode and the potential of the charge storage node. The potential barrier may transfer an overflow portion of image charge from the storage node to the capacitor. The third transistor may transfer the overflow charge from the capacitor to the floating diffusion. The capacitor may shield the storage node from image light or may reflect at least some of the image light towards the photodiode.

An image sensor is provided including a pixel array, a correlated double sampling (CDS) unit, an analog-digital converting (ADC) unit, a control unit, and an overflow power voltage control unit. The pixel array includes at least one unit pixel that generates accumulated charges corresponding to incident light in a photoelectric conversion period and outputs an analog signal based on the accumulated charges in a readout period. The CDS unit generates an image signal by performing a CDS operation on the analog signal. An ADC unit converts the image signal into a digital signal. A control unit controls the pixel array, the CDS unit, and the ADC unit. An overflow power voltage control unit controls an overflow power voltage to have a low voltage level in the photoelectric conversion period and controls the overflow power voltage to have a high voltage level in the readout period.

The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

A photoelectric conversion device includes a pixel array including pixels arranged in rows and columns, each of the pixels being configured to output a pixel signal, and including an optical filter and a photoelectric conversion unit, wherein the optical filters of different colors are arranged for each rows and each columns, a holding circuit including first holding units for each of the columns, the first holding units being configured to respectively hold the pixel signals read out from the pixels including the optical filters of different colors in one column of the pixel array in parallel, an output signal line, and a readout circuit configured to successively read out the pixel signals of pixels including the optical filters of the same color from the first holding units for each of the columns to the output signal line.

An array sensor and a method for forming and operating the same are provided. The array sensor includes: a sensor circuit including an array of pixel units that includes N rows of pixel units; and a driving circuit including at least N rows of shifting units; where the driving circuit further includes: a first global clearing signal line connected with odd rows of shifting units, a signal of which being applied to trigger the odd rows of shifting units to simultaneously turn on odd rows of pixel units, so that the odd rows of pixel units simultaneously discharge residual charge; and a second global clearing signal line connected with even rows of shifting units, a signal of which being applied to trigger the even rows of shifting units to simultaneously turn on even rows of pixel units, so that the even rows of pixel units simultaneously discharge residual charge.

A high dynamic range imaging pixel may include a photodiode that generates charge in response to incident light. When the generated charge exceeds a first charge level, the charge may overflow through a first transistor to a first storage capacitor. When the generated charge exceeds a second charge level that is higher than the first charge level, the charge may overflow through a second transistor. The charge that overflows through the second transistor may alternately be coupled to a voltage supply and drained or transferred to a second storage capacitor for subsequent readout. Diverting more overflow charge to the voltage supply may increase the dynamic range of the pixel. The amount of charge diverted to the voltage supply may therefore be updated to control the dynamic range of the imaging pixel.