An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

A device and method of fabricating a device having depletion-mode and enhancement-mode high-electron-mobility transistors (HEMTs) on a single wafer are disclosed. The method of fabrication involves providing semiconductor layers capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMT, forming a series of trenches and fins in the semiconductor layers over an active area of the semiconductor layers on which a gate contact terminal is to be set down, the fins of respective HEMTs having different widths resulting in different voltage thresholds for the respective depletion-mode HEMTs.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

A double-channel semiconductor device is presented herein. The double-channel semiconductor device is a cascode solution integrating two semiconductor channels: a HEMT channel (104) and a thin film transistor (TFT) channel (216). The HEMT channel can be an AIGaN/GaN HEMT channel and the TFT channel can be a polycrystalline silicon (polysilicon) TFT channel. The polysilicon TFT may advantageously operate in enhancement mode to realize an enhancement-mode cascode device.

A double-channel semiconductor device is presented herein. The double-channel semiconductor device is a cascode solution integrating two semiconductor channels: a HEMT channel (104) and a thin film transistor (TFT) channel (216). The HEMT channel can be an AIGaN/GaN HEMT channel and the TFT channel can be a polycrystalline silicon (polysilicon) TFT channel. The polysilicon TFT may advantageously operate in enhancement mode to realize an enhancement-mode cascode device.

A driving circuit includes a first driving device configured to drive a power device, a first precharge circuit and a first predriving circuit. The first predriving circuit is electrically connected to the first precharge circuit and the first driving device. The first precharge circuit is configured to, in response to an input signal of the driving circuit having a first signal level, generate a first precharging voltage. The first precharge circuit is further configured to, in response to the input signal having a second signal level different from the first signal level, fully turn on, based on the first precharging voltage, a first device in the first precharge circuit to supply a first boost voltage to the first predriving circuit to drive the first driving device.

A driving circuit includes a first driving device configured to drive a power device, a first precharge circuit and a first predriving circuit. The first predriving circuit is electrically connected to the first precharge circuit and the first driving device. The first precharge circuit is configured to, in response to an input signal of the driving circuit having a first signal level, generate a first precharging voltage. The first precharge circuit is further configured to, in response to the input signal having a second signal level different from the first signal level, fully turn on, based on the first precharging voltage, a first device in the first precharge circuit to supply a first boost voltage to the first predriving circuit to drive the first driving device.

Disclosed are a semiconductor structure and a fabricating method thereof. The semiconductor structure includes a substrate, a channel layer, a barrier layer and a first P-type semiconductor layer stacked sequentially, the channel layer and the barrier layer form a heterojunction, and the 2DEG at the channel may be depleted by the first P-type semiconductor layer, so as to implement an enhancement mode device; and a sidewall of the first P-type semiconductor layer, a sidewall of the aluminum-containing film layer, and a sidewall of the gate contact layer that are aligned are stacked sequentially on the barrier layer in a gate region, and a material of the aluminum-containing film layer includes at least any one of AlN, AlON or Al.sub.2O.sub.3.