A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

A semiconductor component includes semiconductor fins formed between a base plane and a main surface of a semiconductor body. Each semiconductor fin includes a source region formed between the main surface and a channel/body region, and a drift zone formed between the channel/body region and the base plane. The semiconductor component further includes gate electrode structures on two mutually opposite sides of each channel/body region, and a field electrode structure between mutually adjacent ones of the semiconductor fins. Each field electrode structure is separated from the drift zone by a field dielectric and extends from the main surface as far as the base plane. The gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from two sides.

A high bandgap Schottky contact layer device and methods for producing same are provided herein. According to one aspect, a high bandgap Schottky contact layer device comprises a substrate, a first Schottky layer over the substrate, the first Schottky layer having a first bandgap, and a second Schottky layer over the first Schottky layer, the second Schottky layer having a second bandgap. The device further comprises a first metal contact over the second Schottky layer and at least one ohmic contact, a portion of which being in direct contact with the substrate. The first bandgap is greater than 1.7 electronvolts (eV). In one embodiment, the second bandgap is also greater than 1.7 eV.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Provided is a stabilizing circuit structure using a sense field effect transistor (sense-FET). A power semiconductor module includes a depletion-mode field effect transistor (D-mode FET) and the sense FET that has same structure as the D-mode FET and varies in area. Also the power semiconductor module includes not only an enhancement-mode field effect transistor (E-mode FET), but also the stabilizing circuit including circuit elements such as a resistor, a capacitor, an inductor, or a diode.

A semiconductor device includes a high side driver, in which the high side driver has an output transistor configured to supply a power voltage to an output terminal based on a driving voltage applied to a gate electrode of the output transistor; a short circuit transistor configured to couple the gate electrode of the output transistor with the output terminal; and a switch transistor connected in series between the gate electrode of the output transistor and a drain electrode of the short circuit transistor. The switch transistor is controlled by a back gate of the switch transistor.

Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

An enhancement-depletion circuit element includes a depletion-mode load transistor and an enhancement-mode drive transistor formed from the common elements of: a first patterned conductive layer including a load gate electrode and a drive gate electrode; a patterned inorganic dielectric stack including a load gate dielectric and a drive gate dielectric; a patterned inorganic semiconductor layer including a load semiconductor region and a drive semiconductor region; a second patterned conductive layer including a load source, a load drain, a drive source and a drive drain; and a patterned differential passivation structure having a patterned polymer dielectric layer and a patterned conformal inorganic dielectric layer. The depletion-mode load transistor has a load back-channel in contact with the patterned conformal inorganic dielectric layer. The enhancement-mode drive transistor has a drive back-channel in contact with the patterned polymer dielectric layer.

A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel fog nation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.