A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.

An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals. The second Ill-nitride semiconductor region includes a second heterojunction, a third terminal connected to the second Ill-nitride semiconductor region, a fourth terminal laterally spaced from the third terminal and connected to the second Ill-nitride semiconductor region, first highly doped semiconductor regions of a first conductivity type formed over the second Ill-nitride semiconductor region.

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.

Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch including a III-nitride integrated circuit, the III-nitride integrated circuit including a high voltage HEMT, the high voltage HEMT comprising high voltage HEMT source terminal, a high voltage HEMT drain terminal, and a high voltage HEMT gate terminal, and at least part of an interface circuit. The semiconductor switch includes a high voltage transistor device that includes a transistor device first terminal, a transistor device second terminal, and a transistor device gate terminal, wherein the high voltage HEMT source terminal and the transistor device first terminal are operatively connected to the first main terminal, the high voltage HEMT drain terminal and the transistor device second terminal are operatively connected to the second main terminal. The high voltage HEMT gate terminal is operatively connected to the control terminal via the interface circuit.

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first doped nitride semiconductor layer, and a second doped nitride semiconductor layer. The first nitride semiconductor layer is formed on the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and has a band gap greater than a band gap of the first nitride semiconductor layer. The first doped nitride semiconductor layer is formed on the second nitride semiconductor layer. The second doped nitride semiconductor layer is formed on the second nitride semiconductor layer. A dopant of the first doped nitride semiconductor layer is different from a dopant of the second doped nitride semiconductor layer.

A cascode semiconductor device comprise a normally-on high-voltage (HV) silicon carbide (SiC) junction field-effect transistor (JFET), a normally-off low-voltage (LV) gallium nitride (GaN) high-electron-mobility transistor (HEMT) and a clamping circuit. The SiC JFET has a first gate terminal, a first drain terminal and a first source terminal. The GaN HEMT has a second gate terminal, a second drain terminal and a second source terminal. The second drain terminal is connected to the first source terminal. The second source terminal is connected to the first gate terminal. The clamping circuit is connected between the second drain terminal and the second gate terminal and has a clamping voltage. The clamping voltage is greater than a magnitude of a threshold voltage of the SiC JFET and smaller than a reverse gate voltage limit of the SiC JFET.