Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

In one aspect, a method includes etching a magnetic field sensor element covered by a bilayer hardmask. In another aspect, a method includes depositing a silicon nitride on a magnetic field sensor element, depositing a silicon dioxide on the silicon nitride, forming the bilayer mask by etching the silicon dioxide and etching the magnetic field sensor element partially covered by the bilayer hardmask. The magnetic field sensor element includes one of a giant magnetoresistance (GMR) element, a tunneling magnetoresistance (TMR) element or a magnetic tunnel junction (MTJ). The bilayer mask includes the silicon dioxide and the silicon nitride. In a further aspect, a sensor includes a magnetic field sensor element that includes one of a GMR element, a TMR element or a MTJ. The sensor also includes a bilayer hardmask disposed on the magnetic field sensor element. The bilayer mask includes a silicon dioxide and a silicon nitride.

A perpendicular magnetic tunnel junction device (pMTJ) is provided that has a structure of a first heavy metal layer, a first thin dusting layer on the first heavy metal layer, a first CoFeB layer on the thin dusting layer, a MgO barrier layer on the first CoFeB layer, a second CoFeB layer on the MgO barrier layer, a second thin dusting layer on the CoFeB layer; and a second heavy metal layer on the thin dusting layer. The insertion of the thin dusting layer improves thermal stability of the pMTJ structure.

A method of manufacturing a pressure sensor comprises: above a film portion formed on one surface of a substrate, depositing a first magnetic layer, a second magnetic layer and an intermediate layer between the first and second magnetic layers on one surface of a substrate; removing the deposited layers leaving a part thereof; and removing a part of the substrate from another surface of the substrate. By removing the deposited layers leaving a part thereof, a strain detecting element is formed in a part of a first region, the strain detecting element comprising the first magnetic layer, the second magnetic layer and the intermediate layer. By removing a part of the substrate, a part of the first region of the substrate is removed. In addition, the deposition of the first magnetic layer is performed with the substrate being bended.

Disclosed is a magnetic annealing apparatus including a processing container that performs a magnetic annealing processing on a plurality of substrates accommodated therein in a magnetic field; a substrate holder that holds the plurality of substrates substantially horizontally in the processing container; a division heater including a plurality of sub-division heaters and covering a substantially entire circumferential surface of an outer periphery of a predetermined region of the processing container along a longitudinal direction; a magnet installed to cover an outside of the division heater; and a controller configured to feedback-control a temperature of a predetermined control target heater among the plurality of sub-division heaters, and to control temperatures of the plurality of sub-division heaters other than the predetermined control target heater based on a control output obtained by multiplying a control output of the predetermined control target heater and a predetermined ratio.

Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.

The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. The conductive upper electrode has a lower portion and an upper portion. The lower portion overlies the magnetic tunnel junction and is laterally surrounded by an encapsulation structure. The upper portion is arranged onto the lower portion and the encapsulation structure, and laterally extends past the lower portion of the conductive upper electrode. By laterally extending past the lower portion, the upper portion of the conductive upper electrode gives a via a larger landing area than the lower portion of the upper electrode would provide, thereby mitigating via punch through resulting from overlay errors.

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N.sub.2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N.sub.2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.