Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

A spin-orbit-torque magnetization rotational element includes: a spin-orbit torque wiring layer which extends in an X direction; and a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer, wherein the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and wherein the easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends.

A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

A layered structure which achieves both high spin polarization and low electrical resistance is provided. The layered structure includes a Heusler alloy, and graphene that is in direct contact with the surface of the Heusler alloy. Such a layered structure is fabricated by forming a thin film of the Heusler alloy over a substrate under vacuum, and growing graphene on the surface of the thin film of the Heusler alloy while maintaining the vacuum.

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.

A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

The present disclosure provides a semiconductor structure, including an N.sup.th metal layer over a transistor region, where N is a natural number, and a bottom electrode over the N.sup.th metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1).sup.th metal layer over the top electrode. The first width is greater than the third width.

A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.