A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.

Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. The structure includes a non-volatile memory element having a magnetic-tunneling-junction layer stack. The magnetic-tunneling-junction layer stack has a fixed layer that includes a synthetic antiferromagnetic layer. The structure further includes a via positioned adjacent to the magnetic-tunneling-junction layer stack. The via is comprised of a magnetic material.

A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer.

A phase transformation electronic device comprises: a first conductive layer; a second conductive layer opposite to and spaced from the first conductive layer; a phase transformation material layer disposed between the first conductive layer and the second conductive layer, wherein the phase transformation material layer is formed by a hydrogen-containing transition metal oxide having a structural formula of ABO.sub.xH.sub.y, wherein A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; and an ionic liquid layer disposed between the phase transformation material layer and the first conductive layer, wherein the ionic liquid layer is capable of providing hydrogen ions and oxygen ions.

A magnetic tunnel junction (MTJ) containing device is provided that includes an undercut conductive pedestal structure having a concave sidewall positioned between a bottom electrode and a MTJ pillar. The geometric nature of such a conductive pedestal structure makes the pedestal structure unlikely to be resputtered and deposited on a sidewall of the MTJ pillar, especially the sidewall of the tunnel barrier of the MTJ pillar. Thus, electrical shorts caused by depositing resputtered conductive metal particles on the sidewall of the tunnel barrier of the MTJ pillar are substantially reduced.

A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.

A magnetoresistive device includes a spin-orbit-torque (SOT) electrode layer, and a first magnetic layer, a first non-magnetic layer, and a second magnetic layer sequentially stacked over the SOT electrode layer. An interface layer is located between the SOT electrode layer and the first magnetic layer, and an etch stop layer covers a surface portion of the SOT electrode layer and is located adjacent the interface layer. The interface layer includes a metal having a spin diffusion length that is greater than a thickness of the interface layer, and the etch stop layer includes an oxide or nitride material of the metal.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.

The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.