Circuits, semiconductor devices, and systems are provided. An illustrative circuit includes a first pair of transistors cross-coupled with a second pair of transistors. The circuit may further include a gain control circuit coupled with the first pair of transistors and the second pair of transistors, where the gain control circuit provides an error compensation for a beta variation effect in at least one of the first pair of transistors and the second pair of transistors.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

An integrated circuit (IC) may include a pillar bar disposed in a bar area over a row of transistors to conduct a current through the transistors and to conduct heat away from the transistors. The pillar bar includes a top metal layer, a bottom metal layer coupled to a terminal of each of the transistors in the row, and at least one intermediate layer between the top metal layer and the bottom metal layer. When heated by the transistors, the metal in the pillar bar expands at a different rate than the IC substrate, causing heat-related stress that may damage the IC. In a pillar bar disclosed herein, one of the intermediate layers includes separate metal regions separated by a non-metal material in the bar area. The pillar bar includes a central metal region and separate metal regions between the central metal region and the ends of the pillar bar.

A semiconductor device includes a semiconductor body having first and second surfaces opposite to each other. The semiconductor body includes a first well region having a first conductivity type, second and third well regions spaced apart from each other in a first direction with the first well region interposed therebetween and having a second conductivity type, first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, a second doped region, which is adjacent to the second well region and has the second conductivity type, and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.