A spin current magnetoresistance effect element includes a magnetoresistance effect element, a spin-orbit torque wiring that extends in a first direction intersecting a lamination direction of the magnetoresistance effect element and is positioned on a side of the magnetoresistance effect element with the second ferromagnetic metal layer, and a control unit configured to control a direction of a current during reading. The control unit is connected to at least one of a first and second point, which are positions with the magnetoresistance effect element interposed therebetween in the first direction in the spin-orbit torque wiring, and a third point on a side of the magnetoresistance effect element with the first ferromagnetic layer. The control unit shunts a read current during reading from the third point toward the first point and the second point or merges the read current toward the third point from the first point and the second point.

A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

A device includes a memory cell having a gate-all-around (GAA) transistor and the well strap cell having a dummy fin-like field effect transistor (FinFET). The GAA transistor includes a first fin extending along a first direction, and the dummy FinFET includes a second fin extending along the first direction. The GAA transistor includes first source/drain features over the first fin and suspended channel layers between the first source/drain features. The first source/drain features include a first type dopant. The suspended channel layers have a first channel width along a second direction different than the first direction. The dummy FinFET includes second source/drain features over the second fin and a fin channel layer between the second source/drain features. The second source/drain features include a second type dopant. The fin channel layer has a second channel width along the second direction. The second channel width is greater than the first channel width.

In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

A device includes a memory cell having a gate-all-around (GAA) transistor and the well strap cell having a dummy fin-like field effect transistor (FinFET). The GAA transistor includes a first fin extending along a first direction, and the dummy FinFET includes a second fin extending along the first direction. The GAA transistor includes first source/drain features over the first fin and suspended channel layers between the first source/drain features. The first source/drain features include a first type dopant. The suspended channel layers have a first channel width along a second direction different than the first direction. The dummy FinFET includes second source/drain features over the second fin and a fin channel layer between the second source/drain features. The second source/drain features include a second type dopant. The fin channel layer has a second channel width along the second direction. The second channel width is greater than the first channel width.

Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. The semiconductor device includes a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes first, second, and third substrings of transistors that are arranged along first, second, and third portions of the channel structure, respectively. Gate structures of transistors in the first, second, and third substring are separated by respective first, second, and third insulating layers and the second insulating layers have a higher etch rate than that of the third insulating layers.

This spin current magnetization rotational element includes a first ferromagnetic metal layer for a magnetization direction to be changed, and a spin-orbit torque wiring extending in a second direction intersecting a first direction which is an orthogonal direction to a surface of the first ferromagnetic metal layer and configured to be joined to the first ferromagnetic metal layer, wherein the spin-orbit torque wiring has a structure in which a spin conduction layer joined to the first ferromagnetic metal layer and a spin generation layer joined to the spin conduction layer on a surface on a side opposite to the first ferromagnetic metal layer are laminated.

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

According to an embodiment, a magnetic tunnel junction includes a tunnel barrier layer provided between a first magnetic layer and a second magnetic layer. The tunnel barrier layer is a crystal body made of a stacked structure of a first insulating layer and a second insulating layer. The crystal body is oriented. The first insulating layer is made of an oxide of Mg.sub.1-xX.sub.x (0≤x≤0.15). X includes at least one element selected from the group consisting of Al and Ti. The second insulating layer is made of an oxide of an alloy including at least two elements selected from the group consisting of Mg, Al, Zn, and Li. Both the first magnetic layer and the second magnetic layer are made of an alloy including B and at least one element selected from the group consisting of Co and Fe.