Patent classifications
H10F77/146
Semiconductor photo-receiving device
According to one embodiment, a semiconductor photo-receiving device includes a substrate, a light propagation layer and a semiconductor layer including a lowest layer and upper layers. The upper layers include an optical absorption layer. The light propagation layer includes a first light input layer, a first annular layer at a desired distance from the first light input layer, and a first optical waveguide connecting the first light input layer and annular layer. The lowest layer of the semiconductor layer includes a second light input layer, a second annular layer at a desired distance from the second light input layer, and a second optical waveguide connecting the second light input layer and annular layer.
Tandem nanofilm photovoltaic cells joined by wafer bonding
An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 m to about 10 m. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means.
Optoelectronic Semiconductor Chip and Method for Fabrication Thereof
An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a first semiconductor layer sequence having a plurality of microdiodes, and a second semiconductor layer sequence having an active region. The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
InGaN/GaN multiple quantum well blue light detector combined with embedded electrode and passivation layer structure and preparation method and application thereof
An InGaN/GaN multiple quantum well blue light detector- includes: a Si substrate, an AlN/AlGaN/GaN buffer layer, a u-GaN/AlN/u-GaN/SiN.sub.x/u-GaN buffer layer, an n-GaN buffer layer, an InGaN/GaN superlattice layer and an InGaN/GaN multiple quantum well layer in sequence from bottom to top. The multiple quantum well layer has a groove and a mesa, the mesa and the groove of the multiple quantum well layer are provided with a Si.sub.3N.sub.4 passivation layer. The passivation layer in the groove is provided with a first metal layer electrode with a semicircular cross section, and the passivation layer on the mesa is provided with second metal layer electrode.
Optoelectronic devices including twisted bilayers
An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions. The first and second semiconducting atomically thin layers are located proximate to each other, and an angular difference between the first lattice direction and the second lattice direction is between about 0.000001 and 0.5, or about 0.000001 and 0.5 deviant from of a Vicnal angle of the first and second semiconducting atomically thin layers. Alternatively, or in addition to the above, the first and second semiconducting atomically thin layers may form a Moir superlattice of exciton funnels with a period between about 50 nm to 3 cm. The optoelectronic device may also include charge carrier conductors in electrical communication with the semiconducting atomically thin layers to either inject or extract charge carriers.
All-wavelength (VIS-LWIR) transparent electrical contacts and interconnects and methods of making them
A method for fabricating an optically transparent conductor including depositing a plurality of metal nanowires on a substrate, annealing or illuminating the plurality of metal nanowires to thermally or optically fuse nanowire junctions between metal nanowires to form a metal nanowire network, disposing a graphene layer over the metal nanowire network to form a nanohybrid layer comprising the graphene layer and the metal nanowire network, depositing a dielectric passivation layer over the nanohybrid layer, patterning the dielectric passivation layer using lithography, printing, or any other method of patterning to define an area for the optically transparent conductor, and etching the patterned dielectric passivation layer to define the optically transparent conductor.
DUAL WAVELENGTH IMAGING CELL ARRAY INTEGRATED CIRCUIT
A semiconductor device is provided that includes an array of imaging cells realized from a plurality of layers formed on a substrate, wherein the plurality of layers includes at least one modulation doped quantum well structure spaced from at least one quantum dot structure. Each respective imaging cell includes an imaging region spaced from a corresponding charge storage region. The at least one quantum dot structure of the imaging region generates photocurrent arising from absorption of incident electromagnetic radiation. The at least one modulation doped quantum well structure defines a buried channel for lateral transfer of the photocurrent for charge accumulation in the charge storage region and output therefrom. The at least one modulation doped quantum well structure and the at least one quantum dot structure of each imaging cell can be disposed within a resonant cavity that receives the incident electromagnetic radiation or below a structured metal film having a periodic array of holes.
Heteroepitaxial growth of orientation-patterned materials on orientation-patterned foreign substrates
A method of forming a layered OP material is provided, where the layered OP material comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more.
CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS
A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
Field effect transistor with conduction band electron channel and uni-terminal response
A uni-terminal transistor device is described. In one embodiment, an n-channel transistor having p-terminal characteristics comprises a first semiconductor layer having a discrete hole level; a second semiconductor layer having a conduction band whose minimum level is lower than that of the first semiconductor layer; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level below the minimum level of the conduction band of the second semiconductor layer for zero bias applied to the gate metal layer and to obtain p-terminal characteristics.