The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.

The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers.

After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a substrate, the first finFET and the ESD device. The first finFET is formed such that it includes finFET fins extending from the substrate. The ESD device includes two vertically stacked PN diodes including vertically stacked first, second, third and fourth layers. The first layer is an N doped layer and is disposed directly over the substrate, the second layer is a P doped layer and is disposed directly over the first layer, the third layer is an N doped layer and is disposed directly over the second layer and the fourth layer is a P doped layer and is disposed directly over the third layer.

Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. The nano wire is configured from a first region and a second region. For instance, the first region is intermittently doped with a p-type dopant, and the second region is doped with an n-type dopant.