A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.

Provided is a manufacturing method for a semiconductor device including a transistor portion and a diode portion. The manufacturing method includes forming, on an upper surface of a semiconductor substrate including a bulk donor, an emitter region of the transistor portion and an anode region of the diode portion as an active region, performing ion implantation of a first dopant of a first conductivity type to the transistor portion and the diode portion from a lower surface of the semiconductor substrate, and performing ion implantation of a second dopant of the first conductivity type to the transistor portion from the lower surface of the semiconductor substrate.

A semiconductor device includes: a semiconductor substrate; a plurality of trenches provided on a top surface side of the semiconductor substrate; am insulated gate electrode structure buried inside the respective trenches; an interlayer insulating film deposited on top surfaces of the semiconductor substrate and the insulated gate electrode structure; and a silicide layer deposited at a bottom of a contact hole penetrating the interlayer insulating film so as to be in contact with the top surface of the semiconductor substrate interposed between the trenches adjacent to each other, wherein at least a part of a bottom surface of the silicide layer is located at a higher position than a bottom surface of the interlayer insulating film.

Electronic components, more particularly triacs, are provided. An example triac is formed inside and on top of a semiconductor substrate. The triac comprising: on the side of a first surface of the substrate, a first doped region of a first conductivity type and connected to a first conduction terminal; on the side of a second surface of the substrate opposite to the first surface, a second doped region of the first conductivity type and connected to a second conduction terminal; and a gate region connected to a control terminal. The first and second regions respectively have first and second parallel lateral surfaces. Between the first and second parallel lateral surfaces is a separation region not covered by the first and second regions, the separation region shaped as a strip extending along a first direction inside of the gate region and exhibiting an inflection outside of the gate region.

A method of manufacturing a semiconductor device according to the present disclosure includes: introducing an impurity having a first conductivity type from an upper surface of a semiconductor substrate having the upper surface and a lower surface; forming a metal layer on the upper surface; introducing hydrogen from the lower surface and forming a first semiconductor layer; performing first heat treatment on the semiconductor substrate, and donating the hydrogen introduced into the first semiconductor layer; introducing from the lower surface an impurity of a second conductivity type opposite to the first conductivity type, and forming a second semiconductor layer at a position shallower than a position of the first semiconductor layer; and performing second heat treatment on the semiconductor substrate at a temperature higher than a temperature of the first heat treatment, and applying the second conductivity type to the second semiconductor layer.

Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

A semiconductor device includes first and second electrodes, first to fourth semiconductor regions, first and second control electrodes, and first and second electrode pads. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The fourth semiconductor region is located on a portion of the third semiconductor region. The first control electrode faces the second, third, and fourth semiconductor regions via a first insulating film. The second control electrode faces the second and third semiconductor regions via a second insulating film. The first electrode pad is electrically connected with the first control electrode. The second electrode pad is electrically connected with the second control electrode. The second electrode pad has a different planar shape from the first electrode pad.