Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.

The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

The present disclosure relates to semiconductor based Josephson junctions and their applications within the field of quantum computing, in particular a tuneable Josephson junction device has been used to construct a gateable transmon qubit. One embodiment relates to a Josephson junction comprising an elongated hybrid nanostructure comprising superconductor and semiconductor materials and a weak link, wherein the weak link is formed by a semiconductor segment of the elongated hybrid nanostructure wherein the superconductor material has been removed to provide a semiconductor weak link.

A transparent electrode including: a substrate; a first layer disposed on the substrate, the first layer including a graphene mesh structure, the graphene mesh structure including graphene and a plurality of holes; and a second layer disposed on the first layer, wherein the second layer includes a plurality of conductive nanowires.

According to one embodiment, the transparent conductive film contains a laminated structure including a conductive layer and a transparent polymer layer. The conductive layer contains a metal nanowire and a carbon material including grapheme. The transparent polymer layer contains a transparent polymer having a glass transition temperature of 100 C. or less. The carbon material constitutes one surface of the transparent conductive film.

The present invention generally relates to nanoscale wires for use in sensors and other applications. In various embodiments, a probe comprising a nanotube (or other nanoscale wire) is provided that can be directly inserted into a cell to determine a property of the cell, e.g., an electrical property. In some cases, only the tip of the nanoscale wire is inserted into the cell; this tip may be very small relative to the cell, allowing for very precise study. In some aspects, the tip of the probe is held by a holding member positioned on a substrate, e.g., at an angle, which makes it easier for the probe to be inserted into the cell. The nanoscale wire may also be connected to electrodes and/or form part of a transistor, such that a property of the nanoscale wire, and thus of the cell, may be determined. Such probes may also be useful for studying other samples besides cells. Other aspects of the invention are generally directed to methods of making or using such probes, kits involving such probes, devices involving such probes, or the like.

A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

A conductor including a graphene layer and a method of manufacturing the conductor are provided. The conductor may further include a nano pattern disposed on a substrate, and the graphene layer may be formed on the nano pattern. The nano pattern may have any various shapes and include a material that interacts with the graphene layer. The nano pattern and the graphene layer included in the conductor may interact with each other, such that the electric characteristics of the conductor are maintained while the heat transfer characteristics thereof are improved.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.