Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

A method for manufacturing an integrated circuit device is provided. The method includes depositing a dielectric layer over a substrate; depositing a first gate electrode layer over the dielectric layer; removing a first portion of the dielectric layer to leave an opening between the first gate electrode layer, the substrate, and second portions of the dielectric layer; depositing a first gate dielectric layer, such that the first gate dielectric layer has a first portion in the opening and a second portion over a top surface of the first gate electrode layer; and depositing a semiconductor layer, such that the semiconductor layer has a first portion in the opening and a second portion over a top surface of the first gate dielectric layer.

A semiconductor device includes a substrate including an active region, a first gate electrode on the active region, a second gate electrode between the first gate electrode and the substrate, a first doped region on one side of the first gate electrode, a second doped region on an other side of the first gate electrode, a third doped region on one side of the first doped region, a fourth doped region on one side of the second doped region, and a plurality of wirings spaced apart from the first gate electrode in a first direction, the first gate electrode overlaps with each of the third doped region and the fourth doped region in the first direction, and each of the plurality of first wirings are spaced apart from each other in a second direction and the second direction within an area corresponding to a width of the first gate electrode.

A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.

A device includes a substrate, channel layers over the substrate, a gate dielectric layer around the channel layers, a first work function metal layer around the gate dielectric layer, a second work function metal layer over the first work function metal layer, and a passivation layer between the first work function metal layer and the second work function metal layer. The passivation layer merges in space vertically between adjacent ones of the channel layers.

A semiconductor memory device includes: a back gate electrode, which includes a first conductive pattern, on a substrate; a first gate electrode, which includes a second conductive pattern, on the back gate electrode; and a first semiconductor pattern between the back gate electrode and the first gate electrode, wherein the first conductive pattern and the second conductive pattern include respective materials and/or have respective physical properties different from each other.

A trench field effect transistor (TFET) may include a semiconductor layer having a trench therein, and a superlattice layer in the semiconductor layer extending along bottom and sidewall portions of the trench. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The TFET may further include source and drain regions defining, along with the superlattice layer, a channel region extending between the source and drain regions, and a gate within the trench comprising a gate insulator lining the trench and a gate electrode within the gate insulator.

A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Provided are a semiconductor device, an electronic apparatus including the semiconductor device, and/or a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, an oxide semiconductor layer on the substrate, a first electrode on the oxide semiconductor layer, a second electrode on the oxide semiconductor layer and apart from the first electrode, and a first layer, a second layer, and a third layer in at least one of a region between the oxide semiconductor layer and the first electrode and a region between the oxide semiconductor layer and the second electrode. The second layer includes at least one selected from tantalum oxide, niobium oxide, strontium oxide, and aluminum oxide.