A power semiconductor device and a preparation method therefor. The power semiconductor device comprises: a first lateral current spreading layer (120); and a device layer (130). The device layer (130) comprises: a plurality of active doped regions (1302); and second lateral current spreading layers (1301), without overlapping projections from the second lateral current spreading layer (1301) and the device layer between adjacent active doped regions (1302) in a direction perpendicular to a surface of the semiconductor substrate layer (100), and the doping concentration of the second lateral current spreading layers (1301) is greater than the doping concentration of the drift layer (110). The power semiconductor device takes both low specific on-resistance and high reliability into consideration.

There is provided a semiconductor device with improved yield and performance. The semiconductor device includes a substrate including a first region and a second region and having a first conductivity type, first and second active patterns spaced apart by a first pitch, on the first region, a first gate structure intersecting the first and second active patterns, first epitaxial patterns each having a second conductivity type, different from the first conductivity type, and receiving the same voltage level, on both sides of the first gate structure on each of the first and second active patterns, third and fourth active patterns spaced apart by a second pitch, on the second region, a second gate structure intersecting the third and fourth active patterns, and second epitaxial patterns each having the second conductivity type, on the sides of the second gate structure on each of the third and fourth active patterns, wherein the first pitch is n times the second pitch (where n is a natural number of 2 or greater), and no epitaxial pattern having the second conductivity type is disposed between the first and second active patterns

A semiconductor device includes: a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction; and a body region of a first conductivity type adjoining a sidewall of the trench gate structure along a first lateral direction. The body region includes a first body sub-region adjoining the sidewall, a second body sub-region adjoining the sidewall, and a third body sub-region. The second body sub-region is arranged, along the first lateral direction, between the third body sub-region and the sidewall. An average net doping concentration along the first lateral direction is larger in the third body sub-region than in the second body sub-region. A degree of partial compensation of dopants of the first conductivity type by dopants of a second conductivity type is larger in the second body sub-region than in the third body sub-region.

Provided is a semiconductor device comprising: a semiconductor substrate; an interlayer dielectric film that is above the semiconductor substrate and is provided with a contact hole; a first upper electrode provided above the interlayer dielectric film, and including a first region having a first contact portion that is electrically connected to the first upper electrode via the contact hole, and a second region having a second contact portion that is electrically connected to the first upper electrode via the contact hole, wherein the second contact portion has a higher resistance than that of the first contact portion.

A semiconductor device includes a chip having first and second principal surfaces, an insulating layer covering the first principal surface, and an extending electrode extending on the first principal surface in a first direction. The extending electrode includes a first electrode layer between the insulating layer and the first principal surface and a second electrode layer, electrically connected to the first electrode layer, on the insulating layer. A first element region includes an element electrically connected to the extending electrode. A second element region, adjacent to the first element region in the first direction, crosses the extending electrode. A second trench electrode structure is in the first principal surface, crosses the extending electrode, and extends across the plurality of second element regions adjacent to each other. The extending electrode does not include the first electrode layer and selectively includes the second electrode layer immediately above the second trench electrode structure.

A semiconductor device includes a chip having first and second principal surfaces, with first and second element regions formed on the first surface. A gate extending electrode runs continuously across both element regions in a first direction. A trench gate structure is formed in the first element region and intersects the gate extending electrode. A second trench electrode structure is formed in the second element region, does not intersect the gate extending electrode, and has a terminal portion inside the second element region spaced from the gate extending electrode in a second, intersecting direction. A gate auxiliary trench is formed immediately below a portion of the gate extending electrode near the second element region in the second direction, and a gate auxiliary embedded electrode is provided in the trench through a gate insulating film and electrically connected to the gate extending electrode.

A semiconductor transistor device includes: a gate trench in a SiC semiconductor body; a channel region at a first side wall of the trench; and a diode region at a second side wall of the trench, the side walls lying opposite to each other in a transverse direction. As seen in a vertical cross-section perpendicular to the side walls, a first surface normal n.sub.1, perpendicular to the first side wall and pointing towards the channel region, is rotated between 174 to 178 in relation to a 4H-SiC Crystal a-direction, and a second surface normal n.sub.2, perpendicular to the second side wall and pointing towards the diode region, is rotated between 2 to 6 in relation to the 4H-SiC Crystal a-direction, or n.sub.1 is rotated between 178 to 182 in relation to a 4H-SiC Crystal m-direction and n.sub.2 is rotated between 2 to 2 in relation to the 4H-SiC Crystal m-direction.

A nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a source electrode and a drain electrode, and a doped nitride-based semiconductor layer. The second III-V nitride-based semiconductor layer is disposed over the first III-V nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer. The source electrode and the drain electrode are disposed over the second III-V nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second III-V nitride-based semiconductor layer and between the source electrode and the drain electrode, in which the doped nitride-based semiconductor layer has an aluminum concentration increasing along an upward direction. The gate electrode is disposed over the doped nitride-based semiconductor layer.

A semiconductor device according to the present disclosure includes: a trench located in a semiconductor substrate on a side of a front surface thereof to extend through a base layer, the trench including a top electrode covered with a top oxide film, a bottom electrode covered with a bottom oxide film, and a boundary oxide film located between the top electrode and the bottom electrode, wherein a surface of the top electrode facing the bottom electrode has a recessed shape and includes a prong forming the recessed shape, the prong extends in a width direction of the trench, the prong and the bottom electrode face each other in the width direction of the trench, the top oxide film has a constant film thickness along the base layer and a layer underlying the base layer, and the boundary oxide film has a greater film thickness than the top oxide film.

A semiconductor device according to the present disclosure includes: a semiconductor substrate; a two-stage dummy active trench located in the semiconductor substrate on a side of a front surface thereof, the two-stage dummy active trench including therein a first upper electrode in an upper stage, a first lower electrode in a lower stage, and a first boundary insulating film located between the first upper electrode and the first lower electrode, the first upper electrode being connected to an emitter electrode and covered with a first upper insulating film, the first lower electrode being connected to a gate electrode and covered with a first lower insulating film, wherein a film thickness of the first boundary insulating film is greater than each of a film thickness of the first upper insulating film and a film thickness of the first lower insulating film.