Disclose are a semiconductor structure and a manufacturing method therefor. The semiconductor structure includes: a substrate and a multi-channel heterojunction layer stacked in layers, and a P-type epitaxial layer. The multi-channel heterojunction layer includes a plurality of heterojunction layers, and each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer includes a plurality of grooves. The P-type epitaxial layer includes a plurality of first P-type regions filling the plurality of grooves respectively. By forming a transverse PN junction by two-dimensional electron gas in the heterojunction and the first P-type region, a PN junction depletion region is widened in reverse bias to pinch off a current channel, so that the Schottky junction with low barrier height is effectively shielded, reduction effect of the Schottky barrier is suppressed and a reverse leakage current is controlled, thereby increasing breakdown voltage and maintaining a lower turn-on voltage.

A semiconductor device includes a first wiring region, a cell region, and a first boundary region between the first wiring region and the cell region. The device includes a first electrode, a second electrode, a first wiring part, a semiconductor layer, a first control electrode, a first contact region, and a second contact region. The semiconductor layer includes first to sixth semiconductor regions. The second semiconductor region includes a first boundary semiconductor part located in the first boundary region. The second semiconductor region is of a second conductivity type. The fifth semiconductor region is located in the cell region. The fifth semiconductor region is of the second conductivity type. A second-conductivity-type impurity concentration in the first boundary semiconductor part is less than a second-conductivity-type impurity concentration in the fifth semiconductor region.

Proposed is a power semiconductor device and, more particularly, to a power semiconductor device that prevents a decrease in total current amount due to an increase in the length of a current movement path by ensuring that a P-TOP region formed in a resistance unit is spaced apart from a field oxide film thereabove, thereby forming a current path between the P-TOP region and the field oxide film.

Provided is a semiconductor device including: an interlayer dielectric film provided above a semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a contact portion at which the front surface electrode and the mesa portion are connected in a contact hole of the interlayer dielectric film; and a lifetime adjustment region provided in a front surface side of the semiconductor substrate, where the contact portion includes a first contact portion provided in the transistor portion and a second contact portion provided in the diode portion, and the first contact portion is arranged at an upper side than the second contact portion.

This application is directed to integrating field-effect transistors (FETs) and Schottky barrier diodes (SBDs) on a substrate and forming an integrated and planar semiconductor device. A P-type Metal Oxide Semiconductor (PMOS) transistor and a P-type SBD are formed on the substrate. The P-type SBD is formed by joining a P-type semiconductor and a first barrier metal. A doping concentration of the P-type channel of the PMOS transistor is established concurrently while a first portion of the P-type semiconductor of the SBD is formed. An extended drain structure of the PMOS transistor and a second portion of the P-type semiconductor are concurrently formed on the substrate concurrently. Distinct silicide contact surfaces for the extended drain structure of the PMOS transistor and the first portion and the second portion of the P-type semiconductor of the P-type SBD are formed concurrently.

A semiconductor device including a transistor portion and a diode portion is provided, the semiconductor device including: a plurality of trench portions provided at a front surface of a semiconductor substrate; a drift region of a first conductivity type; a base region of a second conductivity type; an emitter region of the first conductivity type having a higher doping concentration than the drift region; a first contact region of the second conductivity type having a higher doping concentration than the base region; an anode region of the second conductivity type; and a second contact region of the second conductivity type having a higher doping concentration than the anode region, wherein an amount per unit volume of dopants of the second conductivity type in the mesa portion of the diode portion is greater than or equal to that in the mesa portion of the transistor portion.

Provided is a semiconductor device including a transistor portion and a diode portion, including: a plurality of trench portions provided at a front surface of a semiconductor substrate and including a gate trench portion; an emitter region of a first conductivity type provided above a base region and having a doping concentration higher than that of a drift region; and a first accumulation region of the first conductivity type provided below the base region and having a doping concentration higher than that of the drift region; wherein the transistor portion includes a boundary region provided adjacent to the diode portion and including a boundary mesa portion, wherein the boundary region includes the emitter region, a second accumulation region of the first conductivity type having a doping concentration higher than that of the first accumulation region, and the gate trench portion provided in contact with the boundary mesa portion.

The present disclosure relates to semiconductor structures and, more particularly, to a device with improved latch-up immunity and methods of manufacture. The structure includes: a semiconductor substrate including a layer of a first conductivity type; a first semiconductor material over the layer of the first conductivity type, the first semiconductor layer including the first conductivity type and a layer of a second conductivity type; a second semiconductor material of the second conductivity type over the layer of the second conductivity type; and a deep trench isolation structure electrically connecting to the layer of the first conductivity type, the deep trench isolation layer extending through the first semiconductor material and the second semiconductor material.

Semiconductor devices and methods, including metal oxide silicon field effect transistor (MOSFET) devices and methods. The semiconductor device, such as a MOSFET, includes two source regions; a drain region; two body regions, and a buffer region. Each of the two body regions contacts a different one of the two source regions. The buffer region is located between the two body regions, and contacts the two body regions. A doping concentration of the buffer region is less than a doping concentration of the two body regions.

The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer, a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.