An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that are capable of further reducing a turn-on voltage are provided. An epitaxial wafer for a heterojunction bipolar transistor includes a collector layer made of GaAs, a base layer formed on the collector layer and made of InGaAs, and an emitter layer formed on the base layer and made of InGaP, and the base layer has an In composition that decreases from the emitter layer side toward the collector layer side.

A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein.