A string driver device is described in this disclosure. The string driver device includes a semiconductor channel disposed in an upper portion of a semiconductor substrate and a gate dielectric layer disposed above the semiconductor channel. The string driver device also includes a source region and a drain region disposed at opposite sides of the semiconductor channel, each of the source region and the drain region having a corresponding contact disposed thereon. The string driver device further includes a gate that is disposed above the gate dielectric layer and has a first length, and a field plate layer disposed above the gate, the field plate layer having a second length larger than the first length of the gate, wherein the field plate layer includes one or more edge regions extending across the semiconductor channel edge and toward the source region or the drain region.

The semiconductor device includes a chip that includes SiC and has a main surface, a gate electrode that is arranged on the main surface, includes polysilicon, and has an electrode surface, a silicide portion that is partially formed in a surface portion of the electrode surface, and a polysilicon portion that is formed in a portion of the surface portion of the electrode surface other than the silicide portion.

Device structures and methods of forming the same are provided. A device structure according to the present disclosure includes a substrate having a front side and a back side, a fin structure over the front side, a plurality of nanostructures disposed over the fin structure, a gate structure wrapping around each of the plurality of nanostructures, a first doped region disposed over the back side of the substrate, a backside dielectric layer over the first doped region, and a first contact feature extending through the backside dielectric layer to interface the first doped region.

The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor device and methods of manufacture. The structure includes: a gate structure including a gate dielectric material and a gate electrode with a stepped feature; sidewall spacers on sidewalls of the gate electrode, the sidewall spacers including a notched feature adjacent to the gate electrode; and a silicide contact on a surface of the gate electrode, the silicide contact being free of breaks on the surface of the gate electrode.

A method for forming a contact for a source-drain of a gate all around structure incorporates exposing at least a portion of a nanosheet during formation of the contact. A method may include removing a source-drain material to form an exposed portion of a nanosheet material of at least one nanosheet, forming epitaxial contact layers on the source-drain material and the exposed portion of the nanosheet material, forming a silicide contact layer on at least the epitaxial contact layers, and forming a contact with a metal material on the silicide contact layer. In some embodiments, an exposed portion of the nanosheet material comprises an entire end of at least one nanosheet alone or in conjunction with at least a portion of another nanosheet or in conjunction with an entire end of at least one other nanosheet.

An LDMOS includes a substrate. A gate electrode is disposed on the substrate. A first gate dielectric layer is disposed between the gate electrode and the substrate. A second gate dielectric layer includes a first part and a second part. A source is embedded in the substrate at one side of the gate electrode. A drain is embedded in the substrate at the other side of the gate electrode. The second part of the second gate dielectric layer is extended toward the drain along a horizontal direction. The first part is covered by the gate electrode, and the second part is not covered by the gate electrode. Along the horizontal direction, the first part has a first length, and the second part has a second length. The second length is adjustable for adjusting a breakdown voltage of the LDMOS.

An integrated circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) formed in and over a semiconductor substrate. The MOSFET has a gate structure that includes a gate dielectric layer formed the substrate and a gate electrode located over the gate dielectric layer. A pre-metal dielectric layer is over the gate electrode layer, and an electrical contact through the pre-metal dielectric layer connects to the gate electrode. The polysilicon layer has a mean grain size of 50 nanometers (nm) or less.

The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

A power device includes a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof. A silicided polysilicon temperature sensor and silicided polysilicon gate electrode are provided on the first surface. A source region of first conductivity type and a shielding region of second conductivity type are provided in the semiconductor substrate. The shielding region forms a P-N rectifying junction with the source region, and extends between the silicided polysilicon temperature sensor and the second current carrying terminal. A field oxide insulating region is provided, which extends between the shielding region and the silicided polysilicon temperature sensor.