An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

Devices and methods for forming a device are disclosed. The device includes a substrate with a device region having a length and a width direction. An isolation region surrounds the device region of which an isolation edge abuts the device region. A transistor is disposed in the device region. The transistor includes a gate disposed between first and second source/drain (S/D) regions. A silicide block is disposed on the transistor. The silicide block covers at least the isolation edge adjacent to the gate. The silicide block prevents formation of a silicide contact at least at the isolation edge adjacent to the gate.

Disclosed examples include microelectronic devices, e.g. integrated circuits, which include a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, the source region and drain region having an opposite first conductivity type. A channel region having the first conductivity type extends between the source region and the drain region. A gate electrode over the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration. A self-aligned implant is used to simultaneously implant dopants near the source end of the gate electrode and in the semiconductor substrate near the source region.

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bit line structure positioned on the substrate; a plurality of first bit line spacers positioned on sidewalls of the bit line structure; a plurality of second bit line spacers positioned on the plurality of first bit line spacers. The plurality of first bit line spacers include one or more species of vanadium oxide. The plurality of second bit line spacers include silicon nitride, silicon nitride oxide, or silicon oxynitride.

According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.

A semiconductor device includes a vertical power transistor having a plurality of power transistor cells. Each power transistor cell includes a source region at a first main surface of a semiconductor substrate, a drain region at a second main surface of the semiconductor substrate opposite the first main surface, a gate trench extending into the semiconductor substrate from the first main surface, a gate electrode in the gate trench and comprising doped polycrystalline silicon, and a dielectric material separating the gate electrode from the semiconductor substrate. An upper central part of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region that adjoins the doped polycrystalline silicon. A method of producing the semiconductor device is also described.

The disclosure relates to a semiconductor device having a gate electrode in a vertical gate trench and a channel region laterally aside the gate trench. The gate electrode includes an outer gate region made of an outer gate material, a metal inlay region made of a metal material, and a spacer region. The outer gate material and the spacer region are each different from the metal material. The spacer region, the metal inlay region, and the outer gate region are, at least in a vertical section of the gate electrode, consecutively arranged from a center position within the gate electrode laterally outwardly towards the channel region.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000 C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.