In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.

A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.

A tunneling field-effect transistor with an insulated planar gate adjacent to a heterojunction between wide-bandgap semiconductor, such as silicon carbide, and either a narrow band gap material or a high work function metal. The heterojunction may be formed by filling a recess on a silicon carbide planar substrate, for example by etched into an epitaxially grown drift region atop the planar substrate. The low band gap material may be silicon which is deposited heterogeneously and, optionally, annealed via laser treatment and/or doped. The high work function metal may be tungsten, platinum, titanium, nickel, tantalum, or gold, or an alloy containing such a metal. The plane of the gate may be lateral or vertical. A blocking region of opposite doping type from the drift prevents conduction from the filled recess to the drift other than the conduction though the heterojunction.

A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.

A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.

A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate.

A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.

An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region.