A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.

An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device.

A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

A semiconductor disolator device is provided. The device may include a silicon-on-insulator (SOI) substrate, a body layer disposed on the SOI substrate, a first p-type well disposed on the body layer, a first n-type well disposed on the first p-type well to form a first p-n junction, and a second p-type well that is spaced a predetermined distance from at least one of the first p-type well and first n-type well.

In a circuit portion, a p.sup.+-type diffusion region penetrates, in the depth direction, an n.sup.-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p.sup.++-type contact region, an n.sup.+-type diffusion region, and a p.sup.+-type diffusion region are selectively provided in a p.sup.+-type diffusion region on the front side of the base substrate. The p.sup.+-type diffusion region penetrates the p.sup.-type diffusion region in the depth direction, on the outer periphery of the p.sup.-type diffusion region. An n.sup.+-type source region, the p.sup.+-type diffusion region, the p.sup.++-type contact region, and the n.sup.+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

A semiconductor device includes a diode region and an IGBT region. The diode region includes a front side anode region, an n-type diode barrier region, an n-type diode pillar region reaching the diode barrier region through the front side anode region, and a p-type back side anode region separated from the front side anode region by the diode barrier region. The IGBT region includes a front side body region, an n-type IGBT barrier region, and a back side body region separated from the front side body region by the IGBT barrier region. When a gate-off voltage is applied to a gate electrode, a resistance between the IGBT barrier region and the emitter electrode is higher than a resistance between the diode barrier region and the anode electrode.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a top surface. The semiconductor device structure includes a first pillar structure over the substrate. The first pillar structure includes a first heavily n-doped layer, a first p-doped layer, an n-doped layer, and a first heavily p-doped layer, which are sequentially stacked together. The first pillar structure extends in a direction away from the substrate.