Patent classifications
H10D62/128
High power TVS with enhanced repetitive surge performance
A TVS device may include a substrate, comprising a polarity of a first type, a first dopant layer, disposed on a first main surface of the substrate, and comprising a polarity of a second type, wherein the first dopant layer forms a P/N junction with the substrate. The TVS device may further include a second dopant layer, disposed on a second main surface of the substrate, opposite the first main surface, the second layer comprising the polarity of the first type, and a patterned layer, disposed on the second main surface of the substrate, the patterned layer comprising the polarity of the second type, wherein the patterned layer is interspersed with the second layer.
Semiconductor device
Provided is a semiconductor device including: a plurality of trench portions which are provided to positions below a base region from an upper surface of a semiconductor substrate and are arranged next to one another in a first direction on the upper surface of the semiconductor substrate; a first lower end region of a second conductivity type, which is arranged at a first depth position and is provided in contact with a lower end of two or more of the trench portions; and a second lower end region which is arranged at the first depth position and is arranged at a position not overlapping with the first lower end region, in which the second lower end region includes at least one of a region of a first conductivity type or a region of a second conductivity type which has a lower doping concentration than the first lower end region.
Semiconductor device
A semiconductor device includes a semiconductor part, first and second electrodes and first-third and second-third electrodes. The semiconductor part is provided between the first and second electrodes. The semiconductor part includes a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type. The second and third semiconductor layers are arranged between the first layer and the second electrode. The first-third and second-third electrodes are provided in the semiconductor part. The second semiconductor layer is provided between the first-third electrode and the second-third electrode. The second electrode includes a contact portion extending into the second semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer between the contact portion and the second-third electrode. The second semiconductor layer includes a first portion facing the third semiconductor layer via the contact portion.
Electrostatic discharge prevention
The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.