A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a <1-100> crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the <1-100> crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z.sub.1/2 level density of 110.sup.11 cm.sup.3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 110.sup.9 A/cm.sup.2 to 110.sup.4 A/cm.sup.2 in a rated voltage V.sub.R.

An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the first boundary trench and the second boundary trench and a first and second IGBT regions. An emitter region and a body region are provided in each of the first and second IGBT regions. Each body region includes a body contact portion. An anode region is provided in the diode region. The anode region includes an anode contact portion. An interval between the first and second boundary trenches is equal to or longer than 200 m. An area ratio of the anode contact portion in the diode region is lower than each of an area ratio of the body contact portion in the first IGBT region and an area ratio of the body contact portion in the second IGBT region.

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.

A semiconductor device of an embodiment includes a SiC layer having a surface inclined with respect to a {000-1} face at an angle of 0 to 10 or a surface a normal line direction of which is inclined with respect to a <000-1> direction at an angle of 80 to 90, a gate electrode, an insulating layer at least a part of which is provided between the surface and the gate electrode, and a region, at least apart of which is provided between the surface and the insulating layer, including a bond between carbon and carbon.

In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.