A process for preparing alloy products powders is described using a self-sustaining or self-propagating SHS-type combustion process. Binary, ternary and quaternary alloy having cadmium, selenium and optionally a third element X or Y selected from Group VIA (such as S or Te) or from group IIB (such as Zn or Hg). The alloy products may be doped or not with a wide variety of other elements. The process involves heating to ignition, maintaining an elevated temperature less than melting for homogenization, followed by cooling and crushing. An optional de-oxidation process may follow to further purify the alloy and balance the stoichiometry.

A P-type solar cell comprises a layer stack with: a back electrode, a p-type semiconductor absorber layer disposed on the back electrode, a crystalline cadmium sulfide (CdS) layer disposed on the absorber layer, and a front electrode disposed on the side of the layer stack opposite of the back electrode. The CdS layer has Cu-doping and a layer thickness between 50 and 300 . A method for producing a p-type solar cell comprises: providing a p-type photoactive semiconductor absorber layer, etching the surface of the absorber layer such that crystallographic unevenness and pinholes are reduced, depositing a CdS layer on the absorber layer, with a layer thickness between 50 and 200 , heating at least the CdS layer to recrystallize the CdS layer, and optionally placing on the absorber layer a Cu-containing layer different from the CdS layer, either after etching or after the application of the CdS layer.

A P-type solar cell comprises a layer stack with: a back electrode, a p-type semiconductor absorber layer disposed on the back electrode, a crystalline cadmium sulfide (CdS) layer disposed on the absorber layer, and a front electrode disposed on the side of the layer stack opposite the back electrode. The CdS layer has Cu-doping and a layer thickness between 50 and 300 . A method for producing a p-type solar cell comprises: providing a p-type photoactive semiconductor absorber layer, etching the surface of the absorber layer such that crystallographic unevenness and pinholes are reduced, depositing a CdS layer on the absorber layer, with a layer thickness between 50 and 200 , applying heat to at least the CdS layer to recrystallize the CdS layer, and optionally placing on the absorber layer a Cu-containing layer different from the CdS layer, either after etching or after the application of the CdS layer.

A method is provided for fabricating a thin-film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor material. This pre-reaction typically includes processing above the liquidus temperature of the compound semiconductor. The compound semiconductor material is reduced to a particulate form and deposited onto a substrate to form a thin-film having a composition and atomic structure substantially the same as a composition and atomic structure of the compound semiconductor material.

An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

A multi-junction photovoltaic cell includes a substrate and a back contact layer formed on the substrate. A low bandgap Group IB-IIIB-VIB.sub.2 material solar absorber layer is formed on the back contact layer. A heterojunction partner layer is formed on the low bandgap solar absorber layer, to help form the bottom cell junction, and the heterojunction partner layer includes at least one layer of a high resistivity material having a resistivity of at least 100 ohms-centimeter. The high resistivity material has the formula (Zn and/or Mg)(S, Se, O, and/or OH). A conductive interconnect layer is formed above the heterojunction partner layer, and at least one additional single-junction photovoltaic cell is formed on the conductive interconnect layer, as a top cell. The top cell may have an amorphous Silicon or p-type Cadmium Selenide solar absorber layer. Cadmium Selenide may be converted from n-type to p-type with a chloride doping process.